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Application-specific integrated circuit (ASIC) for use in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Architecture and method for testing of an integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Architecture for built-in self-test of parallel optical...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Architecture of an efficient at-speed programmable memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Architecture, circuitry and method for testing one or more...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Area efficient memory architecture with decoder self test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Area optimized edge-triggered flip-flop for high-speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Arithmetic built-in self-test of multiple scan-based...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Arrangement and method of testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Arrangement and method of testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Arrangement for testing integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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ASIC BIST employing stored indications of completion

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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ASIC logic BIST employing registers seeded with differing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Assembly and method for testing integrated circuit devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Assembly for LSI test and method for the test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous bist for embedded multiport memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous communication apparatus using JTAG test data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous debug interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Asynchronous set-reset circuit device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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