Salphasic timing calibration system for an integrated circuit te
Sampling rate converter for both oversampling and...
Saving debugging contexts with periodic built-in self-test...
Scalable columnar boundary scan architecture for integrated...
Scaling logic for event based test system
Scan architecture for full custom blocks
Scan architecture for full custom blocks with improved scan...
Scan based automatic test pattern generation (ATPG) test...
Scan based testing of an integrated circuit containing...
Scan capable dual edge-triggered state element for...
Scan cell circuit and scan chain consisting of same for test...
Scan cells with minimized shoot-through and scan chains and...
Scan chain architecture for increased diagnostic capability...
Scan chain cell with delay testing capability
Scan chain circuit and method
Scan chain connectivity
Scan chain design using skewed clocks
Scan chain diagnostics using logic paths
Scan chain disable function for power saving
Scan chain extracting method, test apparatus, circuit...