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Radio frequency identification transponder integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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RAM functional test facilitation circuit with reduced scale

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Random path delay testing methodology

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Random pattern weight control by pseudo random bit pattern...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Rapid fail analysis of embedded objects

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Re-programmable COMSEC module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Read only memory embedded in a dynamic random access memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Reading data from a memory with a memory access controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Real time function view system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Real-time decoder for scan test patterns

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reception data synchronizing apparatus and method, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reconfigurable built-in self-test engine for testing a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reconfigurable device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reconfigurable programmable logic system with configuration...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reconstruction engine for a hardware circuit emulator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Reconstruction of non-deterministic algorithmic tester...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Recovery from errors in a data processing apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reduced pattern memory in digital test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reduced pin count scan chain implementation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reduced power testing with equally divided scan paths

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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