Arrangement for testing integrated circuits

Details Arrangement for testing integrated circuits Arrangement for testing integrated circuits

2001-08-17

2009-02-17

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S732000, C714S733000

Reexamination Certificate

active

07493542

ABSTRACT:
The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector generator (4) which generates test vectors in real time so as to transfer these vectors to the circuit (1) to be tested.

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