Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-30
2002-08-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
06430718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an architecture, circuitry and method for testing one or more integrated circuits, each of which implements a test access port (“TAP”) such as the JTAG access port described in IEEE Std 1149.1. The test circuitry can place test signals in parallel upon an integrated circuit, shift the test signals through boundary scan cells while using the serialized boundary scan architecture, and thereafter dispatch the test results in parallel from the integrated circuit.
2. Description of the Related Art
Testing an integrated circuit can be performed in various ways. For example, the integrated circuit can be tested while in wafer form using test probe operation. Additionally, or alternatively, the integrated circuit can be tested after it is scribed and packaged. In either instance, sequential and/or combinatorial logic of the integrated circuit must be tested using input test data, generally referred to as “test vectors.” Test vectors are supplied from a commercial test machine or automated test equipment (“ATE”). Alternatively, the test vectors can be provided from circuitry upon the integrated circuit. Such circuitry is often referred to as built in self test (“BIST”) circuitry. BIST circuitry may use a pseudo-random sequence generator to produce test vectors forwarded to the functional core logic of the integrated circuit.
BIST has been used successfully on a number of integrated circuits. However, BIST is difficult to use when testing arbitrary random logic, and requires adding significant test circuitry to the integrated circuit area. If BIST is not used and the test vectors are applied from an external ATE, it is desirable that the test vectors not only verify the integrated circuit operation but also the integrated circuit as it exists on a printed circuit board.
In the early 1990's, a standard was developed and approved as IEEE Std. 1149.1 and 1149.1a, henceforth referred to as the JTAG standard. The JTAG standard was envisioned to allow testing of the integrated circuit after it had been assembled onto the printed circuit board. Moreover, the JTAG standard provided for testing numerous integrated circuits on the board as well as the interconnect of those circuits to the printed conductors of the board. In-system testing was therefore provided for testing the entire, assembled printed circuit board using pins associated with a test access port (“TAP”).
An integrated circuit that is JTAG compliant will have reserved a four or five signal TAP. If testing of the integrated circuit involves a boundary scan mechanism, then each integrated circuit also contains one or more boundary scan cells and a TAP controller for orchestrating signal flow within and through each of those cells.
FIG. 1
illustrates a printed circuit board
10
having multiple integrated circuits
12
,
14
, and
16
mounted thereon. For sake of brevity, only three integrated circuits are shown. However, it is recognized that a printed circuit board may embody certainly more than three integrated circuits.
FIG. 1
also illustrates three input conductors
18
and three output conductors
20
associated with integrated circuit
14
. Almost all integrated circuits are known to include more than three input conductors (or pins), and more than three output conductors (or pins). Therefore,
FIG. 1
is used only as an abbreviated example so as not to unduly complicate the drawing.
Coupled between the input pins and the to-be-tested core logic
22
are respective boundary scan cells
24
. Likewise boundary scan cells
26
are shown between core logic
22
and the output pins. Depending on the state of TAP controller
28
, each boundary scan cell can either allow core logic
22
to be connected to external integrated circuits
12
and/or
16
, or can enable boundary scan testing from a test data input conductor, TDI. TDI along with the test data output conductor TDO, the test mode select conductor TMS, and the test clock conductor TCK form four of possibly five pins attributed to TAP. TDI and TDO are daisy-chained through each boundary scan cell
24
and
26
, and from integrated circuit to integrated circuit, whereas TCK and TMS are broadcast. Prior to entering the first of the daisy-chained integrated circuits, signals upon TDI, TDO, TMS, and TCK of the TAP are derived from an ATE.
In addition to boundary scan cells
24
and
26
attributed to each input/output pin, integrated circuit
14
also may include scan elements (SEs)
25
arranged internal to the circuit
14
. Scan elements
25
are chained together and used for internal manufacturing testing of the core logic, for example. Scan elements
25
communicate with corresponding portions of the core logic
22
. Each scan element may receive a bit, and shift that bit to the next scan element in the chain such that when the scan is complete, a multiple number of scan elements contain a rather large test vector comprising a plurality of bits. Thus, the scan elements may be rather numerous and may include more than one chain to facilitate design debug and manufacturing testing. Scan elements
25
are serially accessible from the TDI, TDO, TMS and TCK signals. The IEEE Std 1149.1 specification provides for multiple scan chains, some of which may be known to the integrated circuit manufacturer only. An example by which the scan elements
25
are used arise in programmable logic devices, and are expressed in various data sheets of manufacturers such as Cypress Semiconductor Corp.
Depending on what is placed into a scan chain, its length can be quite large. Shifting test information into or out of a rather long scan register chain can demand a lot of input and output cycles and associated vector memory on the ATE channels assigned to access the TAP pins of the integrated circuit under test. The IEEE Std 1149.1 makes known the use of bypass registers, or identification code (IDCODE) registers on dedicated chains within possibly numerous scan element chains that extend throughout an integrated circuit. While the boundary scan cells
24
and
26
can be parallel accessible through input/output pins, the internal scan elements
25
can only be accessed through the serial chain. Thus, the boundary scan cells may be deemed a specific implementation of the scan technique to test any core logic whatsoever, and scan elements are specific to the core logic across which they are chained together in serial fashion.
FIG. 2
illustrates in more detail the daisy-chaining of multiple integrated circuits
30
that are solder connected to surface-mount pads or vias of a printed circuit board
10
. Depending on the number of integrated circuits having a TAP access, a single serialized test signal stream can be input throughout boundary scan cells
32
a
and
32
b
of each integrated circuit and thereafter placed in parallel within the core logic
34
of those integrated circuits. The test vectors are thereby said to be serially fed and parallel placed (i.e., scanned) into the functional core logic. Conversely, the test vectors can only be sent in series into the scan elements via TDI, and received from the scan elements in series via TDO. The ATE connected to TDI and TDO thereby not only produces the test vectors for testing the assembled printed circuit board, but also reads the test vector results. Details of the JTAG and TAP architecture are provided in the 1149.1 and 1149.1a specification. Further details of boundary scan systems and test vectors forward from an ATE to and from boundary scan cells are provided in U.S. Pat. Nos. 5,751,163 and 5,805,607 (both of which are herein incorporated by reference). It is noted that when describing the serial placement of test vectors into the boundary scan cells, serial placement of test vectors occurs within the internal scan elements—the only difference being that the scan chain of the scan elements can in some instances be much longer than, and have more scan elements than, the boundary scan cells.
While the provisions of JTAG and generally the concept of serially
Conley & Rose & Tayon P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
De'cady Albert
Torres Joseph D.
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