Architecture of an efficient at-speed programmable memory...

Details Architecture of an efficient at-speed programmable memory... Architecture of an efficient at-speed programmable memory...

2007-02-13

2007-02-13

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S720000, C714S030000, C365S201000

Reexamination Certificate

active

10869720

ABSTRACT:
A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to the memory built in self test sequencer module and applying a march test to the embedded memory via the satellite engine module based upon information stored within the instruction buffer. The satellite engine module includes an instruction buffer and a sequence generation engine.

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