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Macro-cell flip-flop with scan-in input

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Maintaining data coherency in multi-clock systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Maintenance free test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Maintenance registers with Boundary Scan interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Manipulation of hardware control status registers via...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Manufacturing testing of hot-plug circuits on a computer...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mapping logic for controlling loading of the select ram of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mapping logic for loading control of crossbar multiplexer...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mask network design for scan-based integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Master controller architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Master-slave-type scanning flip-flop circuit for high-speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Match circuit for performing pattern recognition in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Match circuit for performing pattern recognition in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Means for testing dynamic integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Means scanning scan path parts sequentially and capturing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Means scanning scan path parts sequentially and capturing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measurement circuit and method for serially merging...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measuring bridge-fault coverage for test patterns within...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measuring microprocessor susceptibility to internal noise...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measuring propagation delays of programmable logic devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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