Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-03-09
2004-05-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06735731
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to testing of optical transceivers. More particularly, the invention relates to built-in self-test of parallel optical transceivers.
2. Background of the Related Art
The growth of electronic commerce, particularly via the internet, has produced exponential increases in the demand for communication bandwidth for computer networks as well as data storage and retrieval networks. In response to the communication bandwidth needs, optical fiber-based data communication devices are being developed. Most previously known optical link development has focused on serial transceivers (or transmitters and receivers). Recently, the focus has shifted to development of parallel transceivers because of the potential for high aggregate bandwidth and lower costs. Furthermore, parallel transceivers may be designed to handle data which has not been coded or serialized for transmission, which may replace wired buses and connect computers at higher data rates and over longer distances.
However, reliable manufacture and low-cost testing of parallel transceivers pose a number of problems, and manufacturing yields can be reduced significantly due to increased complexity in both chip and module construction. Since testing equipment for parallel transceivers are generally unavailable, utilizing conventional testing equipment and method designed for testing serial transceivers multiplies the testing time when applied to parallel transceivers. Furthermore, existing test equipment are not designed to handle the electrical interface of DC-coupled transceivers. Also, present limitations of the opto-electronic components also require that full-rate testing of a parallel optical transceiver does not rely on transmission of a full-rate clock signal.
Therefore, there is a need for a built-in self-test (BIST) circuit disposed on a parallel optical transceiver which may be utilized in development and manufacturing test and field debug of the parallel optical transceiver. It is desirable for the BIST to serve as a preliminary screen of proper link functions of the parallel optical transceiver. For debugging purposes, it is further desirable for the BIST to identify the faulty channel(s) of the parallel optical transceiver. It is also desirable for the BIST to exercise optical links with full-rate data patterns that closely resemble those transmitted in typical functional or operational mode.
SUMMARY OF THE INVENTION
One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator connected to one or more transmitter channels, a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels, the one or more error detection circuits configured to receive the half-rate clock signal. Each error detection circuit may comprise a first scan chain comprising a plurality of rising-edge-triggered flip-flops configured to receive the half-rate clock signal, a second scan chain comprising a plurality of falling-edge-triggered flip-flops configured to receive the half-rate clock signal, and an error output connected to the first and second scan chains.
Another embodiment provides an apparatus for testing a parallel optical transceiver, comprising: a full-rate clock test pattern generator connected to one or more transmitter channels of the parallel optical transceiver; a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels; an error detector comprising one or more error detection circuits connected to one or more receiver channels of the parallel optical transceiver, the one or more error detection circuits configured to receive the half-rate clock signal; and a test fixture comprising optical connections connecting outputs of the one or more transmitter channels to inputs of the one or more receiver channels.
Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting full-rate clock test pattern and half-rate clock signal through the one or more transmitter channels to one or more corresponding receiver channels; and detecting error utilizing an error detector comprising one or more error detection circuits connected to the one or more receiver channels, the one or more error detection circuits configured to receive the half-rate clock signal.
REFERENCES:
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patent: 6012855 (2000-01-01), Hahn
patent: 6201829 (2001-03-01), Schneider
Texas Instruments, 1.0Gb to 1.6Gb Small Form-Factor Ethernet Transceiver, Oct. 2000, Texas Instruments, p. 1-18.*
Dallas Semiconductor, 3.3V Bit Error Rate Tester (BERT), Oct. 2000, Dallas Semiconductor, p. 1-22.*
Lin et al., A bist Methodology for at speed testing of data communications Transceivers, 2000, IEEE, p. 216-221.*
U.S. patent application Ser. No. 09/689,758, filed Oct. 13, 2000.
Ewen John F.
Siljenberg David W.
Wilkinson-Gruber Stephen C.
Chase Shelly A
De'cady Albert
International Business Machines - Corporation
Moser Patterson & Sheridan LLP
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