Asynchronous set-reset circuit device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S726000, C326S016000

Reexamination Certificate

active

07941715

ABSTRACT:
An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool may include a pair of logic gates having at least two inputs each, and a logic gate structure coupled upstream from the pair of logic gates. The logic gate structure may be for driving one respective input of the pair of logic gates and may have inputs receiving a pair of test command signals. The asynchronous set-reset circuit device may also include a plurality of feedback connections between outputs of the pair of logic gates and respective inputs of the logic gate structure.

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Wehrfritz, C. H., “Techniques for the Transformation of Logic Equations”, May 1974, IEEE Transactions on Computers, vol. c-23, No. 5. pp. 477-480.

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