Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-10-21
2003-12-30
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
06671842
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular a method and apparatus for testing embedded asynchronous multiport memories.
2. Description of the Related Art
It is common practice for the manufacturers of memory chips to test the functionality of the memories at the manufacturing site. After the chips have been tested and certified for shipment, upon sale to the users, the users generally depend upon the reliability of the chips for their own systems to function properly. As the line width of memory cells within a memory array circuit chip continue to shrink (now at less than half a micron), this reliability becomes more difficult to achieve. One of the challenges for the manufacturers of memory devices, is to increase memory capacity without decreasing chip yields due to malfunctioning parts.
Before the memory chips are released for shipment, they typically undergo testing to verify that the support circuitry for the memory array and each of the memory cells within the memory array is functioning properly. This testing method is routinely done because it is not uncommon for a significant percentage of the memory cells within the chip to fail, either because of manufacturing defects or degradation faults.
One standard way for testing chip memories involves using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. An external memory tester supplies power and applies test patterns to the chip to detect faults. External memory testers can only test a limited number of chips at a time, and the test speed is limited by the external bus speed. Consequently, this method of testing is expensive, both in terms of equipment costs and time requirements.
Partly to address these issues, and partly to provide off-site testing, built-in self-testers (BIST) have been incorporated into memory chips as a matter of course. Automated test equipment can now be simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the memory chip, and to monitor a single output signal from the chip. The on-board BIST unit generates all the test patterns and asserts the output signal if the chip passes the functionality test. The BIST can be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
The BIST unit operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a BIST unit writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the BIST unit is able to determine whether the memory cell is faulty. Several classes of fault detection methods are well known, as illustrated by E. R. Hnatek in “4-Kilobit Memories Present a Challenge to Testing”,
Computer Design
, May 1975, pp. 117-125, which is hereby incorporated herein by reference. As Hnatek discusses, there are several considerations that should be taken into account when selecting a fault detection method, including fault coverage and length of the test procedure. Also, since no practical method provides complete coverage, the suitability of the various methods for detecting particular types of faults should be considered.
Multiport memories present special BIST challenges, in that the various ports need to be exercised simultaneously to verify functionality. One BIST for multiport memories is taught by U.S. patent application Ser. No. 09/363,697 entitled “Detecting Interport Faults in Multiport Static Memories” by inventors J. Zhao, et al., which is hereby incorporated herein by reference. The existing multiport BIST techniques of which the author is aware are similar to single port techniques, except that provisions are made to ensure detection of short circuits between the word lines or bit lines of different ports. Such techniques have proven inadequate, as they fail to detect high-resistivity “bridges” that can nonetheless cause the memory array to operate incorrectly. As these faults are regrettably not uncommon, an improved multiport memory BIST is needed to prevent faulty chips from leaving the factory.
SUMMARY OF THE INVENTION
Accordingly, there is disclosed herein a method and apparatus for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults. Accordingly, the clock skew is preferably set to a selected value or is swept across a selected skew range which is determined to cause the desired effect.
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Crosby Thompson W.
Irrinki V. Swamy
Phan Tuan
Chaudry Mujtaba
Conley Rose
De'cady Albert
LSI Logic Corporation
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