Asynchronous integrated circuit tester

Details Asynchronous integrated circuit tester Asynchronous integrated circuit tester

1998-04-27

2000-08-08

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

061016225

ABSTRACT:
An asynchronous integrated circuit (IC) tester includes a set of channels interconnected by a runtime bus. Each channel accesses a separate terminal of an IC device under test (DUT) for carrying out test activities during successive cycles of a test. During each cycle of a test, each channel may transmit a test signal to the DUT, sample a DUT output signal and store sample data representing the logic state of the DUT output signal, and/or compare previously stored sample data to expected patterns to determine if the DUT is operating correctly. Any channel may be programmed to place a MATCH code on the runtime bus when it recognizes, or fails to recognize, a particular logic pattern in the DUT output signal. Other channels may be programmed to pause their comparison activities until they receive the MATCH code over the runtime bus. Thus a DUT output signal event detected by any one channel triggers test activities by other channels.

REFERENCES:
patent: 5835506 (1998-11-01), Kuglin
patent: 5948115 (1999-09-01), Dinteman
Narayanan, Asynchronous Multiple Scan Chanis, IEEE, pg. 270-276, 1995.

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