Area efficient memory architecture with decoder self test...

Details Area efficient memory architecture with decoder self test... Area efficient memory architecture with decoder self test...

2006-05-18

2011-10-25

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S742000

Reexamination Certificate

active

08046655

ABSTRACT:
An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.

REFERENCES:
patent: 3995215 (1976-11-01), Chu et al.
patent: 4639919 (1987-01-01), Chang et al.
patent: 5331644 (1994-07-01), Ishii et al.
patent: 5689514 (1997-11-01), Saitoh
patent: 6064244 (2000-05-01), Wakayama et al.
patent: 6072719 (2000-06-01), Tanzawa et al.
patent: 6072737 (2000-06-01), Morgan et al.
patent: 6191998 (2001-02-01), Reddy et al.
patent: 6470475 (2002-10-01), Dubey
patent: 6721216 (2004-04-01), Mak et al.
patent: 6743536 (2004-06-01), Fuglevand
patent: 6745799 (2004-06-01), Fuglevand
patent: 6773839 (2004-08-01), Fuglevand et al.
patent: 6805987 (2004-10-01), Bai et al.
patent: 6806678 (2004-10-01), Holmes
patent: 6811906 (2004-11-01), Bai et al.
patent: 6828050 (2004-12-01), Bai et al.
patent: 6858335 (2005-02-01), Schmidt et al.
patent: 6912166 (2005-06-01), Kawai et al.
patent: 6922803 (2005-07-01), Nakao et al.
patent: 6939636 (2005-09-01), Fuglevand et al.
patent: 6982129 (2006-01-01), Bai et al.
patent: WO 03/058733 (2003-07-01), None
patent: WO 03/063283 (2003-07-01), None

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