LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling,Digital logic testing

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ABIST data compression and serialization for memory built-in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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ABIST data compression and serialization for memory built-in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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ABIST-assisted detection of scan chain defects

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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AC coupled line testing using boundary scan test methodology

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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AC coupled line testing using boundary scan test methodology

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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AC LSSD/LBIST test coverage enhancement

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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AC propagation testing preventing sampling test data at...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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AC scan diagnostic method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accelerated scan circuitry and method for reducing scan test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accelerated scan circuitry and method for reducing scan test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accelerated scan circuitry and method for reducing scan test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accelerating scan test by re-using response data as stimulus...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accelerating scan test by re-using response data as stimulus...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Access method for embedded JTAG TAP controller instruction...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accessing sequential data in a microcontroller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accessing sequential data in a microcontroller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accessing test modes using command sequences

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Accurately identifying failing scan bits in compression...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Achieving desired synchronization at sequential elements...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Achieving desired synchronization at sequential elements...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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