Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-26
2007-06-26
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C327S202000
Reexamination Certificate
active
10996161
ABSTRACT:
An area optimized edge-triggered flip-flop for high-speed memory dominated design is provided. The area optimized flip-flop also provides a bypass mode. The bypass mode allows the area optimized flip-flops to act like a buffer. This allows the area optimized flip-flop to provide the basic functionality of a flip-flop during standard operation, but also allows the area optimized flip-flop to act like a buffer when desirable, such as during modes of testing of the design. The area optimized flip-flop provides most of the functionality of a typical flip-flop, while reducing the total area and power consumption of the design.
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De'cady Albert
Marvell International Ltd.
Trimmings John P.
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