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D flip-flop structure with flush path for high-speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data accelerator and methods for increasing data throughput

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data alignment for telecommunications networks

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data carrier module having indication means for indicating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data communication interface with memory access controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data failure memory compaction for semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data log acquisition circuit and data log acquisition method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data processing apparatus for IC tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data processing device test apparatus and method therefor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data processing system and method for debugging a JavaScript pro

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data processing system external pin connectivity to complex func

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data processing system, circuit arrangement and program product

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data processing with configurable registers

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data retaining boundary scan cell

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data retention latch provision within integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data transfer device and method thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Data transfer validation system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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DDR circuit with addressable TAP linking circuitry and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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DDR gate and delay clock circuitry for parallel interface...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Debug circuit and a method of debugging

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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