Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-10-11
2005-10-11
Wright, Norman M. (Department: 2134)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S046000, C714S715000, C714S727000, C714S728000, C713S152000
Reexamination Certificate
active
06954888
ABSTRACT:
An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.
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Rajski Janusz
Tyszer Jerzy
Klarquist & Sparkman, LLP
Wright Norman M.
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