Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-20
2003-02-04
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06516434
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an application-specific integrated circuit (ASIC) for use in communication facilities of a digital network wherein a data signal to be transmitted is composed of frames.
The invention also relates to a communication facility of a digital network comprising a plurality of application-specific integrated circuits, and to a digital network with communication facilities comprising a plurality of application-specific integrated circuits.
Integrated circuits of the above kind are known in the art in various forms. In one integrated circuit, for example, a switching matrix is implemented in which one or more inlets have access to one or more outlets. Such integrated circuits are used in communications systems for switching purposes, for example. One or more integrated circuits are commonly implemented on a single semiconductor chip that is used in a communication facility, e.g., a transmitter or receiver unit, of a communications network.
In prior-art communications networks, the data signals to be transmitted are usually composed of frames. A frame has an overhead section, containing a frame word for indicating the beginning of the frame, and a payload section. The overhead section contains the data to be transmitted. One example of a standard for the transmission of a data signal with such a frame structure is the synchronous digital hierarchy (SDH) standard. According to this standard, each frame is represented as a 9 row by 270 column matrix. The first 9 columns of the frame form the overhead section, and the remaining 261 columns form the payload section. The first row of the overhead contains the frame word, also referred to as the frame alignment word (FAW), which indicates the beginning of the frame.
With the aid of the frame word, a plausibility check can be performed on the transmitted data. If the frame word is not detected in two successive frames, the integrated circuit will stop the transmission of the data in the frames until it detects the frame word in two successive frames again. In addition, the frame word can be used to assign the data contained in the payload section to individual signal channels.
The frames are commonly transmitted at a frequency of 155 MHz (STM-1 frames). It is also possible to transmit the frames at 622 MHz (STM-4 frames) or 2.4 GHz (STM-16 frames).
In the prior art, the performance of such integrated circuits is tested by means of external testing devices. These testing devices incorporate, for example, a signal generator for generating a test signal and a device for measuring a test signal and detecting bit errors. The testing devices may also be implemented on semiconductor chips that are disposed within the communication facility separately from the integrated circuits of the communication facility. These testing devices implemented on semiconductor chips are connected to the integrated circuits of the communication facility. Such a testing device is described, for example, in an article by Paul K. Sun and Greg Lowe, “XBERT—A Versatile 622 Mb/sec Bit Error Rate Generator/Receiver”, Proceedings Sixth Annual IEEE International ASIC Conference and Exhibit New York, N.Y., USA, 1993.
The testing device disclosed therein processes test signals that are composed of frames. The test signals are used to test the performance of semiconductor circuits that can only process data signals composed of frames. In an article by Dennis T. Kong, “2.488 Gb/s SONET Multiplexer/Demultiplexer with Frame Detection Capability”, IEEE Journal on Selected Areas in Communications, Vol. 9, No. 5, June 1991, an optical transmission network is described in which the data signal to be transmitted is composed of frames. The article describes various framing methods.
The prior-art integrated circuits have the disadvantage of requiring external testing devices for making performance tests.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to improve an integrated circuit of the above kind in such a way that external testing devices for testing the integrated circuit can be dispensed with.
To attain this object, the invention provides an integrated circuit of the above kind which is characterized in that it comprises a circuit for executing the ASIC functions and a data test circuit having first means for generating a test signal composed of frames and second means for detecting bit errors in a received test signal.
The integrated circuit according to the invention includes a circuit for executing the ASIC functions. This circuit executes the functions of conventional ASICs as are known from the prior art. The integrated circuit according to the invention further includes a data test circuit. By means of the data test circuit, the performance of the circuit for executing the ASIC functions or of the entire integrated circuit can be tested quickly and easily without additional testing devices. In this way, the cost and complexity of the performance test of an integrated circuit can be significantly reduced.
The testing of the integrated circuit can take place prior to the start-up of the communication facility containing the integrated circuit or, at no major additional cost, during the operation of the communication facility. This makes it possible to monitor the integrated circuit on-line or at least at arbitrary instants during the operation of the communication facility.
The additional costs of the data test circuit incorporated in the integrated circuit according to the invention are considerably lower than the costs of a separate testing device as is known from the prior art. Also, the cost of the design and layout of the integrated circuit incorporating the data test circuit is considerably lower than the cost of testing the performance of an integrated circuit by means of a separate testing device.
The data test circuit of the integrated circuit according to the invention generates a test signal composed of frames. This makes it possible to test the performance of such integrated circuits, which use data signals composed of frames, quickly and in a simple manner.
If the data test circuit is of a suitable design, the integrated circuit according to the invention can also be used to test the entire superordinate circuit of a communication facility, which incorporates the integrated circuit. To accomplish this, in a preferred embodiment of the invention, the first means of the data test circuit are connected to at least one output of the integrated circuit. The first means generate a framed test signal which is passed through the output section of the superordinate circuit. At the output of the superordinate circuit, the test signal is then fed to an external measuring device or the like which compares the received test signal with a reference signal. The reference signal corresponds to an error-free test signal. In this way, the output section of the superordinate circuit can be tested.
In another preferred embodiment of the invention, the second means of the data test circuit are connected to an input of the integrated circuit. According to this embodiment, a framed test signal can be generated by an external signal generator, for example. The test signal is applied to the input of the superordinate circuit and passes through the input section of the latter to the second means of the data test circuit of the integrated circuit which is incorporated in the superordinate circuit. In the second means, the received test signal is compared with a reference signal corresponding to an error-free test signal. In this way, the input section of a superordinate circuit can be tested.
It is also possible, however, to couple the output of the superordinate circuit externally to the input of the superordinate circuit. Then, the test signal generated by the first means of the data test circuit is passed through the output section of the superordinate circuit to the output, from there to the input, and then through the input section of the superordinate circuit to the second means. In this way, the input s
Stadlhofer Josef
Willekes Elmar
Alcatel
Ton David
LandOfFree
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