Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-28
2006-11-28
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000
Reexamination Certificate
active
07143322
ABSTRACT:
In an arrangement for testing an integrated circuit comprising a combinational logic system, which arrangement performs a test of the behavior of the combinational logic system in comparison with test software which emulates the nominal behavior of the integrated circuit, the signal edge behavior of the combination logic system is checked in that that the test software comprises two identical software models of the combinational logic system to be tested, in which a test sample is applied for test purposes to a first of these software models and whose output signals are coupled to a second of these software models, in that the integrated circuit comprises a test circuit which, in a test mode, applies a first test sample in a first test clock cycle to the input of the combinational logic system of the integrated circuit and takes over the output signal in a buffer memory and which feeds back this output signal as a second test sample in a second test clock cycle to the input of the combinational logic system and again takes over the output signal of the combinational logic system in the buffer memory, and in that at the end of the second test clock cycle, the arrangement compares the results of the combinational logic system of the integrated circuit in the buffer memory with the results of the second software model.
REFERENCES:
patent: 4366393 (1982-12-01), Kasuya
patent: 5377197 (1994-12-01), Patel et al.
patent: 5677916 (1997-10-01), Nozuyama
“Design of Scan-Based Path Delay Testable Sequential Circuits”, Pramanick et al., Oct. 17-21, 1993, IEEE, International Test Conference, pp. 962-971.
“Compact Two-Pattern Test Set Generation for Combinational and Full Scan Circuits”, Hamzaoglu et al., Test Conference Proceedings, Oct. 18-23, 1998, pp. 944-953.
De'cady Albert
Trimmings John P.
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