Scan cell circuit and scan chain consisting of same for test...

Details Scan cell circuit and scan chain consisting of same for test... Scan cell circuit and scan chain consisting of same for test...

2005-12-06

2005-12-06

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S742000

Reexamination Certificate

active

06973609

ABSTRACT:
A scan cell circuit for use in an integrated circuit chip is disclosed. The scan cell circuit includes a multiplexer receiving a first signal, a second signal and a selection signal, and outputting one of the first signal and the second signal in response to the selection signal, and a host circuit electrically connected to the multiplexer, receiving and processing an output of the multiplexer, and proceeding an optional output from a first output end and/or a second output end. When the multiplexer selects the second signal to be outputted in response to a specific state of the selection signal, the first signal output end is fixed at a constant level according to the specific state of the selection signal.

REFERENCES:
patent: 6266801 (2001-07-01), Jin
patent: 6314539 (2001-11-01), Jacobson et al.
patent: 6442721 (2002-08-01), Whetsel
patent: 6446230 (2002-09-01), Chung
patent: 6578168 (2003-06-01), Parulkar et al.
patent: 6611934 (2003-08-01), Whetsel, Jr.

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