Scan based automatic test pattern generation (ATPG) test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reexamination Certificate

active

07343536

ABSTRACT:
A scan based Automatic Test Pattern Generation (ATPG) test circuit, a test method using the test method, and a scan chain reordering method are disclosed. The test circuit tests for scan chains comprising unknown values which could adversely influence a test result. The test circuit uses a scan test point circuit to prevent unknown values from propagating through the test circuit, thus keeping the unknown values from influencing the test result. The reordering method is used where two scan chains comprising an unknown value exist in a single scan cycle so that the unknown values can be located during different clock cycles.

REFERENCES:
patent: 2003/0056164 (2003-03-01), Lauga
patent: 2003/0115521 (2003-06-01), Rajski et al.
patent: 2003/0182604 (2003-09-01), Hathaway et al.
patent: 2004/0064771 (2004-04-01), Appinger et al.
patent: 2006/0101316 (2006-05-01), Wang et al.
patent: 2006/0156122 (2006-07-01), Wang et al.
patent: 2003-194886 (2003-07-01), None
patent: WO 01/33238 (2001-05-01), None

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