Scan chain extracting method, test apparatus, circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S729000

Reexamination Certificate

active

07581149

ABSTRACT:
A scan-chain extracting method of the present invention includes a defining step of defining control-circuit scan chains provided in a test control circuit; an initial-value setting step of setting an initial value for the sequence circuit devices of the control-circuit scan chains; a state setting step of setting the scan chains to through states; an extracting step of extracting data regarding the scan chains; a determining step of determining whether or not data regarding all the scan chains have been extracted; and a changing step of changing the initial value for the sequence circuit devices included in the test control circuit connected to the sequence circuit devices located at the start points of the scan chains, when it is determined that not all data regarding the scan chains have been extracted.

REFERENCES:
patent: 5828579 (1998-10-01), Beausang
patent: 5860105 (1999-01-01), McDermott et al.
patent: 6185721 (2001-02-01), Hosokawa
patent: 6557129 (2003-04-01), Rajski et al.
patent: 6567943 (2003-05-01), Barnhart et al.
patent: 6671870 (2003-12-01), Souef et al.
patent: 6970815 (2005-11-01), Bombal et al.
patent: 7234090 (2007-06-01), Blasi et al.
patent: 7386775 (2008-06-01), Birmiwal et al.
patent: 2002/0124217 (2002-09-01), Hiraide et al.
patent: 2003/0115522 (2003-06-01), Nadeau-Dostie et al.
patent: 2005/0229123 (2005-10-01), Wang et al.
patent: 5-19022 (1993-01-01), None
patent: 5-40151 (1993-02-01), None
patent: 11-66109 (1999-03-01), None
patent: 2002-236144 (2002-08-01), None
patent: 2004-178153 (2004-06-01), None
Jas et al., “Hybrid BIST Based on Weighted Pseudo-Random Testing: a New Test Resource Partitioning Scheme”, IEEE Proceedings, VTS 2001,Apr. 29-May 3, 2001, pp. 2-8.
Barnhart et al., “OPMISR: The Foundation for Compressed ATPG Vectors”, IEEE Proceedings TC 2001, Oct. 30-Nov. 1, 2001.
“A design for testability technique for RTL circuits usingcontrol/data flow extraction” Ghosh et al. Computer-Aided Design, 1996, ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on Publication Date: Nov. 10-14, 1996 On pp. 329-336 ISBN: 0-8186-7597-7 INSPEC Accession No. 5465437.

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