Scaling logic for event based test system

Details Scaling logic for event based test system Scaling logic for event based test system

1999-04-05

2003-04-29

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06557133

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor devices, and more particularly, to a scaling logic to be used in an event based semiconductor test system for generating various test events including test signals and strobe signals of various timings to evaluate a semiconductor device under test wherein the timing of each of the events is defined by a time length from the previous event.
BACKGROUND OF THE INVENTION
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed, i.e., sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system. In a cycle based test system, the semiconductor device under test (DUT) is tested by providing cycled pin pattern vectors at a programmed data rate (tester cycle) to a formatter with timing edges to produce the desired waveforms of the test signals and the strobe signals.
Various timings of the tester cycles, test signals and strobe signals noted above are generated based on a reference clock. The reference clock is produced by a high stability oscillator, for example, a crystal oscillator provided in the IC tester. When the required timing resolution in an IC tester is equal to or an integer multiple of the highest clock rate (shortest clock cycle) of the reference clock oscillator, variety of timing signals can be generated by simply dividing the reference clock by a counter or a divider.
However, IC testers are usually required to have timing resolution higher than the highest clock rate, i.e., the shortest time period, of the reference (system) clock. For example, in the case where a reference clock used in an IC tester is 10 ns (nanosecond), but the IC tester needs to have timing resolution of 0.3 ns or higher, it is not possible to achieve such timing resolution by simply applying or dividing the reference clock. Furthermore, the IC testers today are required to dynamically change such various timings in a cycle by cycle basis based on a test program.
To generate such timing signals, it is known in the prior art that such timings are described by timing data in a test program. For describing the timings with the resolution higher than the reference clock rate, the timing data is described by a combination of an integer multiple of the reference clock time interval (integral part) and a fraction of the reference clock cycle (fractional part). Such timing data is stored in a timing memory and read out at each cycle of the test cycle. Thus, in each test cycle, test signals and strobe signals are generated with reference to the test cycle, such as a start point of each cycle, based on the timing data.
There is another type of test system called an event based test system wherein the desired test signals and strobe signals are produced by data from an event memory directly on a per pin basis. As of today, an event based test system is not commercialized in the market but is still under the feasibility study. The present invention is mainly directed to such an event based test system.
In an event based test system, notion of events is employed, which is any changes of the logic state in signals to be used for testing a semiconductor device under test. For example, such changes are rising and falling of test signals and strobe signals. The timings of the events are defined with respect to a time length from a reference time point. Typically, such reference time points are timings of the previous events.
For producing high resolution timings, the time length (delay value) between the events is defined by a combination of an integer multiple of a reference clock cycle (integer part or event count) and a fraction of the reference clock cycle (fractional part or event vernier). A timing relationship between the event count and the event vernier is shown in timing charts of FIG.
2
. In this example, a reference clock (master clock or system clock) of
FIG. 2A
has a clock cycle (period or time interval) T. Timings of Event
0
, Event
1
and Event
2
of
FIG. 2C
are related as shown in
FIGS. 2A-2C
. To describe Event
1
with reference to Event
0
, the timing relationship of
FIG. 2B
is used in which NT denotes the event count which is N times of the reference clock period T and &Dgr;T denotes the event vernier which is a fraction of the reference clock period T.
In an event based test system, since the timing data in a timing memory (event memory) does not need to include complicated information regarding each and every test cycle data, the description of the timing data can be dramatically simplified. In the event based test system, the timing data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Since such a time difference between the adjacent events is very small, a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
Moreover, in computer aided design (CAD) systems widely used today for designing a semiconductor device such as an LSI and VLSI, a logic simulator in the CAD system utilizes event based test signals for evaluating the semiconductor device. Therefore, an event based test system shows a better linking ability between the design data produced by the CAD system in the design stage and the test signals to be generated using the design data.
As noted above, in an event based test system, the event data in the event memory is expressed by a time difference (delta time) between the current event and the previous event. Thus, to produce events based upon the event data, an event based test system must be able to calculate the sum of the delays up to each event. This requires a logic in the test system to keep counting of the delay times expressed in the event count and to sum the event vernier values.
Such a relationship is shown in a timing chart of
FIG. 3
in which Events
0
-
7
are expressed with reference to the reference clock having a time interval T=1. For example, a delta time &Dgr;V
0
for Event 0 may be 0.75 (event count “0”, and event vernier “0.75”), and a delta time &Dgr;V
1
, for Event
1
may be 1.50 (event count “1”, and event vernier “0.50”). In this situation, the total delay of Event
1
will be 2.25 where a logic in the test system counts two event clocks “2.0” and calculates sum of event vernier “0.25” as the remaining fractional delay. This summing operation is essential for calculating the correct vernier during each event involved in a test signal.
An event test system must also be able to scale the delta times from the event memory. The scaling operation of the delta times &Dgr;V
0
, &Dgr;V
1
. . . &Dgr;V
n
consists of multiplying each delta time by a scaling factor. For example, to scale a delta time of “1.5” by a scale factor of “2” means that 1.5×2=3.0. Generally, for the delta time (delay value) defined by the event count and event vernier as above, this multiplication would consist of (event count+event vernier)×(Scale factor)=Scaled delay.
Software can perform the above noted operations of summing and scaling. However, the time required to transform a large data base of delays, as well as, the time to reload this data into an event based tester may be prohibitive. Rather, the summing and scaling operation may be implemented directly by hardware. A variety of scaling technologies may be feasible in the event based test system.
SUMMARY OF THE INVENTION
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