Scan cells with minimized shoot-through and scan chains and...

Details Scan cells with minimized shoot-through and scan chains and... Scan cells with minimized shoot-through and scan chains and...

2008-05-23

2010-06-29

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000, C714S731000, C327S202000, C327S212000

Reexamination Certificate

active

07747917

ABSTRACT:
A scan including data and shift inputs, and input selection circuitry for selecting between the data and shift inputs during normal, capture, and shift modes in response to only a first control signal and a second control signal. The input selection circuitry includes a first storage element for storing a bit representing a state of the first control signal in response to a change in state of the second control signals and multiplexing circuitry. The multiplexing circuitry is operable in the normal mode to select the data input in response to a first state of the second control signal, in the capture mode to select the data input when the bit stored in the first storage element represents a first state of the first control signal, and in the shift mode to select the shift input when the bit stored in the first storage element represents a second state of the first control signal. A second storage element stores, in response to the first state of the first control signal, data presented at the selected one of the data and shift inputs.

REFERENCES:
patent: 5784384 (1998-07-01), Maeno
patent: 6081913 (2000-06-01), Narayanan et al.
patent: 7197681 (2007-03-01), Dervisoglu et al.

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