Scan chain design using skewed clocks

Details Scan chain design using skewed clocks Scan chain design using skewed clocks

2005-11-08

2005-11-08

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000

Reexamination Certificate

active

06964002

ABSTRACT:
A scan chain comprising a series of flip-flops and two clock signals, where each clock signal is coupled to alternating flip-flops in the series. The second clock signal is typically 180 degrees out of phase with the first clock signal. The two clock signals may be generated from a base clock signal that is coupled to two clocking devices. The first clock signal is output from one clocking device and the second clock signal is output from the other. One clocking device typically passes the base clock signal without delay and the second typically delays it. The clocking devices may be MUXes that can be switched to place the clock signals in or out of phase. The scan chain can be incorporated within an integrated circuit wherein the clock signals are out of phase during testing of the integrated circuit and are in phase after testing of the integrated circuit is complete.

REFERENCES:
patent: 5347523 (1994-09-01), Khatri et al.
patent: 5444405 (1995-08-01), Truong et al.
patent: 5689517 (1997-11-01), Ruparel
patent: 5701335 (1997-12-01), Neudeck
patent: 5818276 (1998-10-01), Garrity et al.
patent: 6816991 (2004-11-01), Sanghani

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