Scalable columnar boundary scan architecture for integrated...

Details Scalable columnar boundary scan architecture for integrated... Scalable columnar boundary scan architecture for integrated...

2006-08-03

2008-11-11

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

07451369

ABSTRACT:
An integrated circuit having a scalable boundary scan architecture. Logic elements, each including at least one data storage element, are arranged in rows and columns. A data distribution system couples the data storage elements together to form a boundary scan chain that traverses the columns in order, e.g., a first column, then a second column, and so forth, from top to bottom in each column. A clock distribution system is coupled to each of the data storage elements in the chain, and provides a clock signal to the first and second columns, again from top to bottom. The clock distribution system provides the clock signal to the top of the second column prior to providing it to the top of the first column. In some embodiments, an additional flip-flop is added to the boundary scan chain for each logic element, to increase the overall operating frequency of the scan chain.

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patent: 7327161 (2008-02-01), Jang et al.
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patent: 2004/0250185 (2004-12-01), Date
Xilinx, Inc.; “Virtex-4 Configuration Guide”; UG071 (v1.4); Jan. 24, 2006; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 57-65.

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