Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-14
2011-06-14
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000, C702S120000
Reexamination Certificate
active
07962811
ABSTRACT:
An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
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Dhong Sang Hoo
Silberman Joel Abraham
Takahashi Osamu
Warnock James Douglas
Wendel Dieter
Gaffin Jeffrey A
International Business Machines - Corporation
Merant Guerrier
Talpia Matthew B.
Walder, Jr. Stephen J.
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