Scan chain architecture for increased diagnostic capability...

Details Scan chain architecture for increased diagnostic capability... Scan chain architecture for increased diagnostic capability...

2011-03-01

2011-03-01

Beausoliel, Robert (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

07900103

ABSTRACT:
A scan chain architecture includes a cascade of flip-flop cells each having at least one input and output or an inverted output. The output or inverted output of a flip-flop is connected to the input of the subsequent flip-flop. The connection between two consecutive flip-flops of the scan chain is selected according to the status of a given flip-flop cell, the status of a previous cell, and the status of the connection between these cells.

REFERENCES:
patent: 5313470 (1994-05-01), Simpson
patent: 5488318 (1996-01-01), Vajapey et al.
patent: 6453436 (2002-09-01), Rizzolo et al.
patent: 6895540 (2005-05-01), Chen et al.
patent: 2005/0108604 (2005-05-01), Wong
patent: 2005/0235184 (2005-10-01), Yamauchi
patent: 2005/0283691 (2005-12-01), Chae
patent: 2007/0168798 (2007-07-01), Cooke

Affiliated with

Also associated with

Rating

Scan chain architecture for increased diagnostic capability... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scan chain architecture for increased diagnostic capability..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan chain architecture for increased diagnostic capability... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2673162