Scan chain cell with delay testing capability

Details Scan chain cell with delay testing capability Scan chain cell with delay testing capability

2011-03-22

2011-03-22

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

07913131

ABSTRACT:
A scan chain cell24is provided with a built-in delay testing capability. An inverter32generates an inverted form of the cell output which is available within the scan chain cell24for rapid use in forming a transition at the cell output Q. Clock gating circuitry36, 38is responsive to a hold signal to block the functional path34, 26, 28through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell24for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry18can be performed.

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Tekumalla, R.; Menon, P.R.; , “Delay-testable non-scan sequential circuits with clock suppression ,” Circuits and Systems, 1996. ISCAS '96., ‘Connecting the World’., 1996 IEEE International Symposium on , vol. 4, No., pp. 137-140 vol. 4, May 12-15, 1996 doi: 10.1109/ISCAS.1996.541918.
Vermaak et al., Using the Oscillation Test Method to Test for Delay Faults in Embedded Cores, (2004), pp. 1105-1110.

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