Scan based testing of an integrated circuit containing...

Details Scan based testing of an integrated circuit containing... Scan based testing of an integrated circuit containing...

2008-10-08

2009-11-24

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07624322

ABSTRACT:
An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory element of another clock domain during a scan based testing of an integrated circuit. In an embodiment, the encoder receives a test clock, including a capture pulse during a capture mode of the scan test, but forwards the capture pulse only to one of the clock domains and blocking the capture pulse to other clock domains. As a result, erroneous captures in the memory element receiving data from another clock domain is avoided without the need of closing timing on paths which are not functionally exercised.

REFERENCES:
patent: 6877123 (2005-04-01), Johnston et al.
patent: 7194669 (2007-03-01), Nadeau-Dostie
patent: 7451371 (2008-11-01), Wang et al.
patent: 7541961 (2009-06-01), Garg
patent: 2008/0320348 (2008-12-01), Ayres et al.

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