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Selected: P

Partitioned pseudo-random logic test for improved...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Partitioning and reordering methods for static test sequence com

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Path test signal generator and checker for use in a digital tran

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern and method of metal line package level test for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern data transfer circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generating method, pattern generator using the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator and electric part testing apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator and memory testing device using the same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator and test apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator for a semiconductor integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator for semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator for semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator for semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern generator for use in a semiconductor test device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pattern matching to validate and classify computer variables...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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PC and ATE integrated chip test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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PC-connectivity for on-chip memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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PCI express physical layer built-in self test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Performance built-in self test system for a device and a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Performance control of an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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