PC-connectivity for on-chip memory

Details PC-connectivity for on-chip memory PC-connectivity for on-chip memory

2011-01-18

2011-01-18

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

07873886

ABSTRACT:
An interface for converting a traditional scan-chain interface into one where locations in the scan-chain can be read or written to from an addressed interface is provided. The interface of the invention includes a scratch pad memory into which the values at the locations in the scan-chain are copied. Those copies in the scratch pad can be read and written to using an addressed interface and if any are changed the values held in the scratch pad are shifted out to update those in the original locations in the scan-chain.

REFERENCES:
patent: 5347523 (1994-09-01), Khatri et al.
patent: 6691268 (2004-02-01), Chin
patent: 1117100 (2001-07-01), None
patent: 03103778 (1991-04-01), None

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