Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-07-31
2001-03-13
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S722000, C714S742000
Reexamination Certificate
active
06202187
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern generator for use in a semiconductor test device for generating random pattern data to supply to a semiconductor device to be tested.
2. Prior Art
The construction of a conventional pattern generator for use in a semiconductor test device will be described with reference to FIG.
4
.
The pattern generator for use in a semiconductor test device comprises an address generator
10
, a sequential pattern memory
11
, a random pattern memory
12
and a selector
13
. The address generator
10
generates address data
10
a
sequentially or at random in accordance with a previously written program, and supplies them to an input terminal of the sequential pattern memory
11
or an input terminal of the random pattern memory
12
.
The address generator
10
is programmed to output a selection signal
10
b
in the manner of allowing the selector
13
to select data
11
a
outputted from the sequential pattern memory
11
when it generates the address data
10
a
sequentially or allowing the selector
13
to select data
12
a
outputted from the random pattern memory
12
when it generates the address data
10
a
at random.
Respective random pattern data are stored in respective addresses of the sequential pattern memory
11
. The sequential pattern memory
11
is a memory (for example, magnetic tape device, etc.) for executing read and write of data by accessing values of consecutive address data (sequential access) such that values of the address data
10
a
are incremented one by one such as . . . →4096→4097→4098→4099 . . . or same values of the select data
11
a
are repeated such as . . . 4101→4101 →. . .
In cases where the address data
10
a
generated by the address generator
10
are consecutively outputted, the random pattern data
11
a
stored in the sequential pattern memory
11
are outputted from the sequential pattern memory
11
in accordance with input address values and inputted a first input terminal of the selector
13
.
The random pattern memory
12
is a memory (random access memory such as a dynamic RAM, a static RAM) which can arbitrarily access respective addresses, and random pattern data are previously stored in respective addresses like the sequential pattern memory
11
. The random pattern memory
12
outputs the random pattern data
12
a
which are stored therein in accordance with values of address data
10
a
outputted from the address generator
10
and inputs to a second input terminal of the selector
13
. The selector
13
selects either the input data
11
a
or input data
12
a
in response to the selection signal
10
b
and outputs the selected data as random pattern data.
The pattern generator for use in a semiconductor test device writes a program on the address generator
10
appropriately in accordance with the content of test or a semiconductor device to be tested and tests on the semiconductor device to be tested using the random pattern data stored in the sequential pattern memory
11
or the random pattern memory
12
.
However, the sequential pattern memory
11
has generally large capacity but it is late in time for outputting data stored in addresses after the addresses are specified, namely, it is a so-called slow speed memory. On the other hand, the random pattern memory
12
is a high speed memory but it has small capacity compared with the sequential pattern memory
11
. Accordingly, the conventional pattern generator for use in a semiconductor test device requires an expensive memory which runs at high speed and has large capacity for generating random pattern data of high speed with large capacity, and hence it has been difficult to allow the pattern generator to run at high speed, to be small sized and to manufacture at low cost.
SUMMARY OF THE INVENTION
The present invention has been made under the circumstances and has an object to provide a pattern generator for use in a semiconductor test device capable of generating random pattern data having large capacity at high speed using a random access memory which runs at high speed and has low capacity.
To achieve the above object, a first aspect of the present invention comprises a pattern generator for use in a semiconductor test device for supplying random pattern data to a semiconductor device to be tested comprising first memory means for previously storing random pattern data therein, and second memory means for storing parts of random pattern data stored in the first memory means and outputting the same parts to the semiconductor device to be tested.
A second aspect of the present invention is the pattern generator for use in a semiconductor test device of the first aspect of the invention wherein the second memory means includes addressing means for specifying addresses for storing parts of the random pattern data.
A third aspect of the present invention is the pattern generator for use in a semiconductor test device of the first aspect of the invention further comprising selection means for outputting either the random pattern data outputted from the first memory means or the random pattern data outputted from the second memory means to the semiconductor device to be tested.
A fourth aspect of the present invention is the pattern generator for use in a semiconductor test device of the first aspect of the invention wherein the first memory means is a sequential access memory and the second memory means is a random access memory.
REFERENCES:
patent: 5062109 (1991-10-01), Ohshima et al.
patent: 5481671 (1996-01-01), Fujisaki
Ando Electric Co. Ltd.
Flynn ,Thiel, Boutell & Tanis, P.C.
Moise Emmanuel L.
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