Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-11-21
2003-07-29
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S718000
Reexamination Certificate
active
06601204
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a memory tester for testing memories formed, for example, by semiconductor integrated circuits and, more particularly, to a pattern generating method for use in testing memories of the type that respond to a start address to generate burst addresses and hence permits fast write and read. The invention pertains as well to a pattern generator using the pattern generating method, and a memory tester using the pattern generator.
FIG. 6
illustrates in block form the general configuration of an IC tester. Reference character TES denotes generally the IC tester. The IC tester TES comprises a main controller
111
, a pattern generator
112
, a timing generator
113
, a waveform formatter
114
, a logic comparator
115
, a driver
116
, an analog comparator
117
, a failure analysis memory
118
, a logical amplitude reference voltage source
121
, a comparison reference voltage source
122
and a device power source
123
.
The main controller
111
is formed, in general, by a computer system and operates under the control of a test program prepared by a user, controlling the pattern generator
112
and the timing generator
113
. The pattern generator
112
generates test pattern data DT, which is converted by the waveform formatter
114
to a test pattern signal of a waveform that meets specifications of a memory under test
119
. The test pattern signal is provided to the driver
116
wherein It is voltage-amplified to a waveform having an amplitude value set in the logical amplitude reference voltage source
121
. The test pattern signal thus voltage-amplified is then applied to the memory under test
119
for storage therein.
A response signal read out of the memory under test
119
is compared by the analog comparator
117
with a reference voltage fed from the reference voltage source
122
to decide whether the response signal has a predetermined logic level (voltage of a logic “H” or “L”). The response signal decided to be at the predetermined logic level is compared by the logic comparator
115
with expectation data EXP provided from the pattern generator
112
. If a mismatch is found between the response signal and the expectation data EXP, it is decided that memory cell of the address from which the response signal was read out is failing, and upon each occurrence of such a failure, the faulty address is stored in the failure analysis memory
118
for use in deciding, after completion of the test, whether the failed cell is repairable.
FIG. 7
which is drafted by the present inventor, illustrates in block form the internal configuration of the pattern generator
112
which employs, for example, the expectation data generating method disclosed in Japanese Patent Application Laid-Open Gazette 08-036035 (Laid Open Feb. 6, 1996). The pattern generator
112
comprises: a program memory
11
in which there are stored microprograms for pattern generation use; a read address generating part
12
which determines an address for reading out the program memory
11
; an address data generating part
13
which generates address data for input to the memory under test
119
; a mask data generating part
15
which generates mask data MD for bitwise masking of test pattern data to be written into the memory under test
119
; a pattern data generating part
15
which generates pattern data TP; an expectation data generating part
16
which generates from the pattern data TP and the mask data MD the expectation data EXP to be supplied to the logic comparator
115
; and a multiplexer
17
which selects and outputs one of the pattern data TP from the pattern data generating part
15
and the expectation data EXP from the expectation data generating part
16
.
Incidentally, the output from the multiplexer
17
will be identified by DT in the
FIG. 7
example and the following description. Accordingly, DT is the pattern data DT at the write timing of the memory under test
119
and the expectation data EXP at the read timing.
The read address generating part
12
is composed of a program counter PC and a arithmetic logic unit ALU. The read address of the program memory
11
indicated by the program counter PC is subjected to an arithmetic operation, such as an addition or subtraction, based on an operation control instruction PC-C containing an operation value and written in the microprogram which is read out of the program memory
11
for the next test cycle, and the operation result is used to update the value of the program counter PC.
The address data generating part
13
, the mask data generating part
14
and the pattern data generating part
1
5
are each composed of an arithmetic logic unit ALU and a register RG. The values indicated by the registers RG, from which they are output as the address data XB, the mask data MD and the pattern data TP, respectively, are subjected to an arithmetic operation, such as an addition or subtraction, based on operation control instructions XB-C, MD-C and TP-C containing operation values and written in the microprograms which are read out of the program memory
11
for the next test cycle, and the operation results are used to update the values of the registers RG.
The address data XB and the pattern data TP are each converted by the waveform formatter
114
to a signal of a waveform that meets the specifications of the memory under test
119
. Read/write control instruction R/W for the memory under test
119
is read out directly from the program memory
11
, and is similarly converted by the waveform formatter
114
to a signal of a waveform that fulfills the specification of the memory under test
119
, thereafter being input thereto.
Now, a description will be given of the mask data MD that is generated in the mask data generating part
14
. Some memory devices have a bit-wise masked write function that inhibits a write for each bit of write data. In the testing of such a memory, the expectation data generating part
16
is required to generate expectation data EXP that has, at bit positions currently masked with the mask data MD, the same bit data as that written previously but has currently written bit data at currently unmasked bit positions.
The expectation data generating part
16
is specifically designed to satisfy the required with ease. That is, the expectation data generating part
16
is made up of a logic inverter INV and an exclusive OR circuit EOR. The mask data MD is provided via the logic inverter INV to the one input terminal of the exclusive OR circuit EOR, and the pattern data TP from the pattern data generating part
15
is fed to the other input terminal of exclusive OR circuit EOR. The exclusive OR circuit EOR outputs exclusive ORs of corresponding bits of the two pieces of input data.
In the case of effecting a write in the memory under test
119
while masking with the mask data MD and reading out the results of the data written from the memory
119
, the multiplexer
17
selects and outputs expectation data EXP generated in the expectation data generating part
16
by the inversion of a control signal EXP-S to, for example, a logic “1”. This expectation data EXP is provided to the logic comparator
115
.
In the mask data MD the mask bit (a write inhibit bit) has a logic “0” and the non-mask bit (a write enable bit) has a logic “1”. Those bits of the mask data MD given the logic “0” are each inverted to “1” by the inverter INV in the expectation data generating part
16
, and function as a signal for logic inversion of the corresponding bit in the pattern data TP. On the other hand, those bits given the logic “1” are each inverted to “0” by the inverter INV in the expectation data generating part
16
, allowing the corresponding bit in the pattern data TP to be output intact at the logical level of its own. That is, in the expectation data generating part
16
the pattern data TP undergoes logic inversion at the bit positions corresponding to the mask bits of the mask data MD, thereafter being provided as the expectation data EXP.
In the case of writing “0s” in all
Advantest Corporation
Gallagher & Lathrop
Lathrop, Esq. David N.
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