Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-12-05
2000-07-25
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714724, 714744, G01R 3128
Patent
active
060947373
ABSTRACT:
A path test signal generator and checker which can achieve a path test by effectively generating a path test signal in a system handling synchronous transport modules STM-Ns with an order higher than that of the basic interface. A test pattern generator generates a continuous PN pattern intermittently, inserts a predetermined logical value in locations of the section overhead and path overhead in a transmission frame while suspending the generation of the path test signal in those locations, and inserts the continuous PN pattern in the entire columns of the payload of the transmission frame. A path overhead insertion circuit rewrites the predetermined logical value inserted in the location of the path overhead into the path overhead. The multiplex section terminating circuit rewrites the predetermined logical value inserted in the location of the MSOH (multiplex section overhead) to the MSOH, and the logical value inserted in the location of the RSOH (regenerator section overhead) to the RSOH. This ensures to achieve the effective path test by generating the synchronous transport module STM-N which accommodates in the entire columns of its payload the continuous path test signal in the form of PN pattern.
REFERENCES:
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J.C. Newell, "High Speed psuedo-random binary sequence generation for testing and data scrambling in gigabit optical transmission systems", IEE Colloquium on `Gigabit Logic Circuits` (Digest No. 075), London UK, Apr. 3, 1992, pp. 1/1-4.
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Chung Phung M.
OKI Electric Industry Co., Ltd.
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