Pattern data transfer circuit

Details Pattern data transfer circuit Pattern data transfer circuit

1999-07-28

2002-06-25

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S743000

Reexamination Certificate

active

06412087

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a tester such as an IC tester for testing an IC Integrated Circuit), more particularly to a pattern data transfer circuit installed inside the tester for transferring pattern data.
2. Prior Art
Integrated circuits have been recently rapidly employed in various electric equipment. Products such as an IC, an LSI (large Integrated Circuit) are realized by circuits having functions of various elements such as a resistor, a capacitor, a transistor which are formed by printing, evaporating process, and the like. However, there occur slight variations in characteristics among various mass-produced devices. Under the circumstances, a test is performed whether characteristics of an IC, an LSI is up to a given standard or not using an IC tester.
Hereupon, a conventional pattern data transfer circuit used inside an IC tester is now described hereinafter.
FIG. 4
is a block diagram showing a conventional pattern data transfer circuit and an associated circuit connected to this pattern data transfer circuit
1
. As shown in
FIG. 4
, the pattern data transfer circuit
1
comprises a CPU (Central Processing Unit)
2
, a plurality of pattern memories
3
and a plurality of pattern generating circuits
4
. The pattern data transfer circuit
1
is connected to a plurality of waveform shaping circuits
5
and a plurality of pin electronics
6
for testing the operation of a DUT (Device Under Test)
7
. The pattern data transfer circuit
1
is also connected to a memory
8
and a RAM (Random Access Memory)
9
, described later.
The pattern memories
3
, the pattern generating circuits
4
, the waveform shaping circuits
5
and the pin electronics
6
are respectively provided by the number corresponding to the number of tester channels of the IC tester built in the pattern data transfer circuit
1
.
The detail of each component is now described. The DUT
7
is formed of an IC, an LSI, etc. and it is the object to be measured when the IC tester checks the operation of the DUT
7
. Respective input/output pins of the DUT
7
are connected to the pin electronics
6
which are provided every tester channels. The memory
8
stores in advance therein various device programs corresponding to the variety of DUTs
7
. The CPU
2
reads out device programs corresponding to the specified DUT
7
from the memory
8
and stores it in the RAM
9
, thereby controlling hardware components inside the IC tester in accordance with the device programs. The CPU
2
temporarily stores adapter board data, pattern data respectively read out from the memory
8
in CPU memories
2
a
,
2
b
built therein. The function of the CPU
2
except that set forth above is described later.
Next, the adapter board and the pattern data are described These data are used by the device programs.
FIG. 5
shows an example of the adapter board data. The adapter board data are used for specifying tester channels connected to respective input/output pins of the DUT
7
and comprise a plurality of groups composed of respective data of ┌Pin Group┘, ┌Pin Name┘, and ┌Tester Channel┘. The ┌Pin Group┘ is used for dividing the input/output pins of the DUT
7
into those for every attribute and composed of those of “DATA”, “ADDRESS”, “MODE”, “CLOCK” and so forth Exemplified in
FIG. 5
is only the pin group of address (“ADDRESS” in the same figure) and data (“DATA” in the same figure). The ┌Pin Name┘ is an inherent name given to distinguish the respective input/output pins of the DUT
7
from one another. The ┌Tester Channel┘ is data which are assigned to the pin electronics
6
connected to the respective input/output pins of the DUT
7
for distinguishing the tester channels.
The first adapter board data shown in
FIG. 5
relates to a pin having “ADDRESS” included in ┌Pin Group┘ and “A0” given to ┌Pin Name┘ which corresponds to tester channel “1” as ┌Tester Channel┘. Likewise, any pin having “A1” to “A7” as ┌Pin Name┘ has “ADDRESS” included in ┌Pin Group┘ and each pin corresponds to tester channels “4”, “10”, “15”, “31”, “40”, “60”, and “61” as the ┌Tester Channel┘. A pin having “DATA” belonging to ┌Pin Group┘ and “D0” given to ┌Pin Name┘ corresponds to a tester channel “80” as ┌Tester Channel┘. The data following the above data are not illustrated, but they likewise correspond to tester channels as set forth above.
FIG. 6
shows an example of pattern data corresponding to the adapter board data shown in FIG.
5
. Each pattern data is represented by 3-bit data of “HiLO”, “I/O”, and “Strobe Mask”. Respective pattern data are used for controlling output levels of a driver waveform to be inputted to the pins of the DUT
7
(“HiLo” in the same figure) by way of tester channels corresponding to the respective ┌Pin Name┘, presence or absence of the receiving of the waveform outputted from the DUT
7
(“I/O” in the same figure), and presence or absence of decision of High/Low (“Strobe Mask” in the same figure) relative to the received waveform. Values of respective data contained in the pattern data mean as follows.
“HiLo”
“1” → “High”,
“0” → Low
“I/0”
“1” → Input,
“0” → Output
“Strobe Mask”
“1” → Absence of Decision,
“0” → Presence of Decision
For example, pattern data such as “0 output”, “1 output”, “L expectation”, “1 output”, “1 output”, and “H expectation”, . . . , . . . , are given to ┌Tester Channel┘ “1” corresponding to ┌Pin Name┘ “A0”.
As evident from
FIG. 6
, for the “I/O” data and “Strobe Mask” data of the tester channel belonging to the Pin Group “ADDRESS”, the same data are to be used for all the tester channels in the direction of a time axis. The pin group having the pattern common to all tester channels in respective pin groups is sometimes called hereinafter “common pin group”.
Pattern data for every tester channels shown in
FIG. 6
are stored in the pattern memories
3
shown in FIG.
4
. The pattern generating circuits
4
generate pattern data (see “PATTERN DATA” shown in
FIG. 6
) on the basis of data stored in the pattern memories
3
corresponding to the their own tester channels and output the pattern data to the waveform shaping circuits
5
corresponding to the tester channels. The waveform shaping circuits
5
shape the driver waveform necessary for testing the DUT
7
in response to pattern data outputted from the pattern generating circuits
4
and output the shaped driver waveforms to the pin electronics
6
corresponding to the tester channels.
The pin electronics
6
are circuits at the side of the ICs used as interfaces between respective input/output pins of the DUT
7
and connected to the respective input/output pins of the DUT
7
. The pin electronics
6
output the driver waveforms outputted from the waveform shaping circuits
5
to the respective input pins of the DUT
7
and receive waveforms outputted from the respective output pins of the DUT
7
.
Described next along a flow chart in
FIG. 7
is pattern data transfer operation by the pattern data transfer circuit
1
. Described hereinafter is a case of transfer of pattern data (
FIG. 6
) corresponding to respective pins having “A0” to “A7” as ┌Pin Name┘ among the adapter board data (FIG.
5
).
First, the CPU
2
reads out a device program corresponding to the DUT
7
from the memory
8
and transfers it to the RAM
9
, and it transfers the adapter board data and pattern data used by the device program to the CPU memories
2
a
,
2
b
in which these data are temporarily stored.
Next, the CPU
2
recognizes ┌Tester Channel┘ corresponding to “A0” of ┌Pin Name┘ as “1” referring to the adapter board data in the CPU memory
2
a
of the CPU
2
, and selects the tester channel “1” (Step
11
). Then, the CPU
2
extracts “HiLo” data corresponding to ┌Pin Name┘ “A0” referring to pattern data in

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