Pattern generator for semiconductor test system

Details Pattern generator for semiconductor test system Pattern generator for semiconductor test system

2005-07-12

2005-07-12

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S720000, C365S201000, C711S217000

Reexamination Certificate

active

06918075

ABSTRACT:
A pattern generator for semiconductor test system for testing a semiconductor memory device by generating and applying test patterns. The pattern generator is capable of freely generating inversion request signals for inverting the read/write data for specified memory cells for a memory device under test having different total numbers of memory cells between X (row) and Y (column) directions. The locations of specified memory cells are on a diagonal line on an array of memory cells in the memory device under test or on a reverse diagonal line which is perpendicular to the diagonal line.

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