Partitioning and reordering methods for static test sequence com

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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714720, 714728, G01R 3128

Patent

active

059833815

ABSTRACT:
Methods of compacting sequential circuit test vector set by partitioning of faults into hard and easy faults, re-ordering vectors in a test set by moving sequences that detect hard faults to the beginning of the test set, and a combination of partitioning and re-ordering.

REFERENCES:
patent: 5444717 (1995-08-01), Rotker et al.
patent: 5617431 (1997-04-01), Tupurt et al.
Pomeranz et al, "Static Compaction for Two-Pattern Test Sets", The Fourth Asian Test Symposium, IEEE, 1995.
Higami et al, "Static Test Compaction for IDDQ testing of Sequential Circuits", pp. 9-13, IEEE, Mar. 1998.
Guo et al, "on speeding-up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits", pp. 467-471, IEEE, Sep. 1998.

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