Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-11-09
2001-08-28
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C438S011000, C257S048000
Reexamination Certificate
active
06282679
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a pattern and method of a metal line package level test for a semiconductor device, which is capable of efficiently testing characteristic of a metal line.
2. Discussion of the Related Art
There are current, temperature, temperature gradient, and current gradient in main factors which cause electromigration (EM) in a metal line of a semiconductor device. However, taking account of only current and temperature factors, characteristic (lifetime) of the metal line in the semiconductor device is presently tested.
A background art metal line package level test pattern for a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1
a
and
1
b
are layouts of background art metal line package level test patterns for a semiconductor device.
FIG. 1
a
shows a JEDEC test pattern. As shown in
FIG. 1
a,
a connecting area
3
is formed between a current applying pad
1
and a test line
2
. The connecting area
3
has a width which is to be gradually narrowed toward the test line
2
so as to minimize temperature gradient and current gradient during test.
Electromigration of the metal line using the JEDEC test pattern is tested in such a manner that a current is applied to the current applying pad
1
and then a voltage of a voltage sensing area
4
at both ends of the test line
2
is measured.
In the JEDEC test pattern, the connecting area
3
is formed with a gradient to prevent temperature gradient during test. However, the JEDEC test pattern has a problem that fails to completely prevent temperature gradient by Joule heating. In addition, the JEDEC test pattern has a problem that it is likely to cause electromigration as a line width of the connecting area
3
is wider than that of the test line
2
.
FIG. 1
b
shows a Lloyd test pattern. Referring to
FIG. 1
b,
a connecting area
3
having a plurality of narrow lines is formed between a current applying pad
1
and a test line
2
. In the same manner as
FIG. 1
a,
the connecting area
3
has a width which is to be gradually narrowed toward the test line
2
so as to minimize temperature gradient and current gradient during test. A voltage sensing area
4
is formed at both ends of the test line
2
.
Electromigration of the metal line using the Lloyd test pattern is tested in such a manner that a current is applied to the current applying pad
1
and then a voltage of the voltage sensing area
4
is measured.
In the Lloyd test pattern, the gradient connecting area
3
is formed to have the plurality of narrow lines so as to minimize temperature gradient and current gradient during test.
However, since the aforementioned background art metal line package level test patterns fail to effectively prevent temperature gradient and current gradient during the metal line test, in particular, temperature gradient by Joule heating, there exists a problem that the metal line test is not exactly performed.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a pattern and method of a metal line package level test for a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a pattern and method of a metal line package level test for a semiconductor device which efficiently tests characteristic of a metal line.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a metal line package level test pattern for a semiconductor device according to the present invention includes a metal line for test, a current applying pad connected to both ends of the metal line, for applying a current to the metal line, a voltage sensing pattern formed at both ends of the metal line, for sensing a voltage of the metal line, and a heater for varying temperature of the current applying pad.
In another aspect, a method of a metal line package level test pattern for a semiconductor device, including a metal line for test, a current applying pad connected to both ends of the metal line, for applying a current to the metal line, and a voltage sensing pattern formed at both ends of the metal line, for sensing a voltage of the metal line, according to the present invention, includes the steps of applying a current to both ends of the current applying pad, making the temperature of the current applying pad relatively higher than the metal line, and sensing a voltage of the metal line via the voltage sensing pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5264377 (1993-11-01), Chesire et al.
patent: 5801394 (1998-09-01), Isobe
patent: 5846848 (1998-12-01), Chih-Sheng et al.
Harry A. Schafft; “Thermal Analysis of Electromigration Test Structures”; IEEE Transaction on Electron Devices, vol. ED-34, No. 3; Mar. 1987; pp. 664-672.
Keni Hinode; “Dependence of Electromigration Damage on Current Density”; J. Appl.Phys. 74(1), Jul. 1, 1993; pp. 201-206.
M. Shatzkes; “A model for conductor failure considering diffusion concurrently with Electromigraiton resulting in a current exponent of 2”; J. Appl. Phys.59 (11), Jun. 1, 1986; pp. 3890-3893.
Ellis et al., Polycrystalline diamond film flow sensor: Solid-State Sensor and Actuator Workshop, IEEE pp. 132-134, 1990.
LG Semicon Co. Ltd.
Moise Emmanuel L.
Morgan & Lewis & Bockius, LLP
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