Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-21
2006-03-21
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
07017094
ABSTRACT:
A semiconductor device is disclosed that include a built-in self test system. The device comprises a logic function and a self test engine coupled and integrated with the logic device. The device includes a performance code storage coupled and integrated with the logic function. The performance code storage contains at least one critical path pattern that will be run on the logic function to determine the performance of the logic function when the self test engine causes the logic function to be in a performance test mode. In summary, a performance sort/validate integrated custom logic device, like a microprocessor core can be tested without the need for a separate, high-performance tester. A performance built-in self test (PBIST) approach provides a basic test procedure to be utilized within the device. An integrated memory array, such as the L1-cache, is provided wherein a select set of SRAM memory words are preconditioned at the time of manufacture to contain predefined functional patterns.
REFERENCES:
patent: 5286656 (1994-02-01), Keown et al.
patent: 5287202 (1994-02-01), Kumarappan
patent: 5583875 (1996-12-01), Weiss
patent: 5710911 (1998-01-01), Walsh et al.
patent: 5796751 (1998-08-01), Kundu
patent: 5913228 (1999-06-01), Bedarida
patent: 5996097 (1999-11-01), Evans et al.
patent: 6031391 (2000-02-01), Couts-Martin et al.
patent: 6133582 (2000-10-01), Osann, Jr. et al.
patent: 6185712 (2001-02-01), Kirihata et al.
patent: 6351837 (2002-02-01), Huang et al.
patent: 6359818 (2002-03-01), Suzuki
patent: 6365859 (2002-04-01), Yi et al.
patent: 6370676 (2002-04-01), Hayashi et al.
patent: 6496952 (2002-12-01), Osada et al.
patent: 6622269 (2003-09-01), Ngo et al.
patent: 2002/0199142 (2002-12-01), Gefen
patent: 2003/0053358 (2003-03-01), Kundu et al.
patent: 2003/0084389 (2003-05-01), Kottapalli et al.
patent: 61241939 (1986-10-01), None
patent: 3138956 (1991-06-01), None
patent: 2001110867 (2001-04-01), None
T. K. Jaber and K. Shah, “Built-In Self-Test Technique for Speed Sorting of VLSI Chips,”IBM Technical Disclosure Bulletin, vol. 32, No 8B, Jan. 1990.
Al-Assadi Waleed K.
Correale, Jr. Anthony
DeBruyne Les Mark
Dick Thomas Anderson
Grollimund Jay Donnelly
De'cady Albert
Gandhi Dipakkumar
Sawyer Law Group LLP
LandOfFree
Performance built-in self test system for a device and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Performance built-in self test system for a device and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Performance built-in self test system for a device and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3533283