PC and ATE integrated chip test equipment

Details PC and ATE integrated chip test equipment PC and ATE integrated chip test equipment

2005-04-19

2005-04-19

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

06883128

ABSTRACT:
The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.

REFERENCES:
patent: 5164663 (1992-11-01), Alcorn
patent: 6324485 (2001-11-01), Ellis
patent: 6351827 (2002-02-01), Co et al.
patent: 6365859 (2002-04-01), Yi et al.
patent: 6594802 (2003-07-01), Ricchetti et al.

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