Pattern generator for semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S720000, C714S742000, C714S744000

Reexamination Certificate

active

06513138

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a pattern generator to be used in a semiconductor test system for testing semiconductor devices, and more particularly, to a pattern generator which can provide high speed test pattern to a semiconductor device under test by multiplexing two or more parallel test patterns while modifying the test pattern as a function of address signals provided to the device under test.
BACKGROUND OF THE INVENTION
The basic configuration of a semiconductor test system essential to the present invention is briefly explained with reference to the block diagram of
FIG. 3
in which a device to be tested is a semiconductor memory. The detailed explanation is omitted since a basic structure of a semiconductor test system is well known in the art. In
FIG. 3
, the basic elements in the test system includes a pattern generator (PG)
150
, a wave formatter or frame controller (FC), a logic comparator (DC), and a failure memory (FM). A device under test (DUT) receives a test pattern from the wave formatter FC and outputs the resultant response signal to the logic comparator DC.
The pattern generator
150
generates an address signal, a write data signal, a control signal, and an expected value signal. The address signal is provided to the DUT through the wave formatter FC as well as to the failure memory FM. Normally, the address information provided to the DUT and failure memory FM are identical to one another. In a write mode of the memory device under test (DUT), the write data signal is also provided to the DUT after being wave shaped by the wave formatter FC.
At the logic comparator DC, the output signal of the DUT, i.e., the stored data in the memory under test is read out and is compared with the expected value signal provided from the pattern generator
150
. When there arises mismatch between the stored data and the expected value signal, fail signals FD
1
-FDn are produced by the comparator DC which are provided to the failure memory FM.
The failure memory FM has memory addresses corresponding to the addresses of the DUT and thus stores the fail signals FD
1
-FDn in the address locations identical or indicative of the address locations of the DUT causing the fail signals. Thus, as a result of the device testing, by referring to the stored data in the failure memory FM, fail analysis can be performed as to which data bit locations and which address locations of the DUT the fails have occurred.
FIG. 4
shows a basic configuration of the pattern generator related to the subject matter of the present invention. The pattern generator of
FIG. 4
includes a sequence generator
100
, an address signal generator
200
, a data signal generator
300
, and a control signal generator
400
. The outputs of the address generator
200
, data generator
300
and control signal generator
400
are provided to the wave formatter FC of FIG.
3
.
The sequence generator
100
continuously generates sequence data
100
s
for producing an arbitrary test pattern corresponding to a device under test, and provides the sequence data to the address signal generator
200
, the data signal generator
300
, and the control signal generator
400
. The sequence data
100
s
is primarily an address signal with a test rate T to access a memory (
210
,
310
,
410
) provided in each of the above noted three generators.
The address signal generator
200
generates a pattern signal relating to X and Y addresses of the memory under test (DUT). The pattern signal including the X and Y addresses are provided to the wave formatter FC, failure memory FM, and data signal generator
300
. At the wave formatter PC, the pattern signal is wave shaped based on the timing condition of the address pins of the DUT. At the failure memory FM, the pattern signal is used as address data of the failure memory for storing the fail signals produced as a result of the logic comparison by the logic comparator DC.
The data signal generator
300
generates a pattern signal including write data to be stored in the DUT (memory device under test) and expected value data. The pattern signal from the data signal generator
300
is provided to the wave formatter FC and the logic comparator DC. The control signal generator
400
generates a pattern signal including a R/W (read/write) control signal (/WE (write enable), /OE (output enable), /CE (chip enable)) and a driver enable signal (DRE) for controlling the operation of pin electronics (I/O) of the test system and the DUT. The pattern signal from the control signal generator
400
is provided to the pin electronics and DUT through the wave formatter FC.
The configuration and operation of the data signal generator
300
is further explained with reference to
FIGS. 5
,
6
and
7
. As shown in
FIG. 5
, the data signal generator
300
includes a data operation control memory
310
and a data generator
320
. The data operation control memory
310
is a memory to store operation instructions to allow various operations of the data generator
320
as will be described later. The data operation control memory
310
receives the sequence data
100
s
from the sequence generator
100
as an input address data and produces control data
310
s
by reading stored contents in the specified address. The control data
310
s
is provided to the data generator
320
.
The major components of the data generator
320
includes a first data generator
321
a
, a second data generator
321
b
, an address function generator
322
, a data topology controller
323
, a first inverter
325
a
, a second inverter
325
b
, a first topology inverter
326
a
, and a second topology inverter
326
b
. The data topology controller
323
and the topology inverter
326
may not be provided in other types of semiconductor test system.
The first data generator
321
a
and second data generator
321
b
are configured identical to each other. When the test pattern is applied to the DUT in a repetition rate two times higher (double rate mode) than the normal test cycle T, the outputs of the first and second data generators
321
a
and
321
b
are multiplexed by the wave formatter FC. Thus, in such a situation, the first data generator
321
a
is used as an even number pattern generator, and the second data generation
321
b
is used as an odd number pattern generator. Further, in the double rate mode, the first and second data generators
321
a
and
321
a
receive control data
310
s
which are different from one another from the memory
310
.
An output signal
321
as
of the first data generator
321
a
which is formed of n bits is transferred to the output of the data generator
320
as a first data signal
326
as
through the first inverter
325
a
and the first topology inverter
326
a
. Similarly, an output signal
321
bs
of the second data generator
321
a
which is formed of n bits is transferred to the output of the data generator
320
as a second data signal
326
bs
through the second inverter
325
b
and the second topology inverter
326
b
. The first and second data signals
326
a
and
326
b
are in a parallel form signal
300
s
having 2n bits. The output signal
300
s
is combined, for example, parallel-to-serial converted by the formatter FC, to create a n-bit signal having two times higher rate.
The address function generator
322
generates a signal
322
s
indicating inversion information for inverting the data in the first and second inverters
325
a
and
325
b
. The inversion information is created as a function of the input address data. The purpose of the data inversion is to easily generate a specific test pattern to test the relationship between the specified memory cells and the peripheral memory cells physically arranged on the X and Y addresses. The inversion information is thus generated by the address function generator
322
when received an address signal A
200
s
from the address signal generator
200
and the control data
310
s
from the data operation control memory
310
.
Based on the inversion information signal
322
s
from the address function generator
3

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