Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-12
2001-11-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06314540
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing of integrated circuit chips, and more particularly to testing for improved manufacturability. Even more particularly, this invention relates to an improved testing technique for IC chips.
TRADEMARKS
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. and Lotus is a registered trademark of its subsidiary Lotus Development Corporation, an independent subsidiary of International Business Machines Corporation, Armonk, N.Y. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
Very large scale integration (VLSI) logic integrated circuit (IC) chips, also known as microprocessors, contain very large numbers of logic circuits. Testing the many logic circuits in a chip is an important part of the manufacturing process of the chip.
Logic circuits typically include many interconnected logic gates. The various logic gates include, e.g., “AND” gates, “OR” gates, “NAND” gates, “NOR” gates, “NOT” gates, “XOR” gates and so on. A logic circuit has a number of inputs for receiving data, and a number of outputs for outputting data. The logic circuit is designed such that for each input pattern, of a set of one or more input patterns, provided at the inputs of the logic circuit, a corresponding predetermined output pattern is produced at the outputs of the circuit.
If there is a fault or defect in the logic circuit, then for one or more input patterns provided at the inputs of the circuit, the observed output patterns produced at the outputs of the circuit will differ from the expected predetermined output patterns.
One way to test for faults in a logic circuit is to apply each possible input pattern at the inputs of the logic circuit, and to compare the actual output pattern with the expected output pattern. For small numbers of possible input patterns, the cost of storing the expected output patterns and performing this deterministic testing is reasonable. However, for large numbers of possible input patterns, the cost of such deterministic testing is too high.
An alternative method of testing for faults in a logic circuit applies random input test patterns at the inputs of the logic circuit, and compares the actual output patterns with the expected output patterns. The number of random test patterns needed to achieve a selected level of confidence that a logic circuit contains no faults depends on the circuit design.
Another alternative method of testing for faults in a logic circuit applies one or more weighted random input test patterns at the inputs of a logic circuit, and compares the actual output patterns with the expected output patterns. The weights may be uniform across all digits in the test pattern, or the weights may be nonuniform. The weighted random test patterns are selected to achieve, efficiently and at a low cost, a desired level of confidence that the logic circuit contains no faults.
As integrated circuit chip devices have become more densely packed with electronic components and more complex, the need for effectively testing such circuits has become more complex and important. This is especially true of digital logic circuits. In order to provide a mechanism for testing complex circuitry of this type, a number of built-in self test (BIST) methodologies have been employed including level sensitive scan design (LSSD) techniques. LSSD design can be performed in accordance with the teachings of “Level Sensitive Logic System,” U.S. Pat. No. 3,783,254, and “Method of Level Sensitive Testing A Functional Logic System,” U.S. Pat. No. 3,761,695, both to Edward B. Eichelberger and of common assignee to this invention, the contents of which are incorporated herein by reference in their entireties. In the LSSD methodology, a long string of shift register latches (SRLs)is employed in a dual function role which does not detract from normal circuit operation. In particular, a shift register (SR) string provides both normal input during circuit operation and also provides a mechanism for providing test input signals to the circuit for testing purposes. These tests may be employed, for example, immediately subsequent to chip manufacture, and in the field to diagnose error conditions. Depending on the source of input signals to the SRL scan string, either normal operations or test operations can be carried out.
An example testing technique includes initializing a set of latches and generating a set of pseudo-random latch value patterns for all latches in a chip. A clock pulse scans the test pattern and the output is then compared to an expected result. Thereafter, a new set of latch values can be loaded into the latches.
In the testing of VLSI logic chips,i.e. microprocessors, tester time directly affects customer cost. Using pseudo-random pattern generation techniques, such as, e.g., logic built-in self test (LBIST), there is a trade-off between tester time (cost to a customer) and test coverage (quality shipped to the customer). Using more patterns increases test coverage, but the increased number of patterns require longer tester time. The reader is referred to “Built-In Self-Test Support in the IBM Engineering Design system,” by B. L. Keller and T. J. Snethen, in the IBM Journal of Research and Development 34, No 2/3, pages 406-415, March/May 1990, describing the development of software to support the LBIST test technique, the contents of which are incorporated by reference in their entirety.
Software models can predict pattern effectiveness, but they are only an approximation of effectiveness. While test coverage asymptotically increases with a greater number of patterns, it becomes difficult to predict when the limit of pseudo-random logic test (PRLT) effectiveness is reached. An inaccurate prediction can have a large effect on product cost and quality. Conventional testing methods do not provide for reducing tester time and cost while accurately monitoring test pattern effectiveness.
Thus, conventional test pattern selection decisions were based on a software approximation of test effectiveness. Test time was reduced by applying different types of patterns, i.e. deterministic patterns with the added cost of increased tester buffer memory requirements as well as effectiveness uncertainty.
Another conventional solution was to remove patterns assumed to be “not effective enough,” without any empirical backing.
Conventionally, high test coverage with an assumed high effectiveness was achieved only through using large numbers of patterns resulting in long test times.
It is desirable to reduce long test times while maintaining test effectiveness.
SUMMARY OF THE INVENTION
The present invention comprises a method for testing integrated circuit chips, including the steps of generating values for latches for a complete test pattern set, partitioning the complete test pattern set into a plurality of partitioned test pattern subsets, and running the partitioned test pattern subsets against a chip.
A feature of the invention includes a method that simulates a complete pattern set and determines a starting value for each of the plurality of partitioned test pattern subsets. One embodiment includes a feature that uses the starting value for each of the plurality of partitioned test pattern subsets. Another embodiment includes a feature that simulates the entire chip. Another embodiment includes a feature that simulates only the starting values and determines the values of the latches.
In an embodiment of the invention, the plurality of partitioned test pattern subsets are divided in equal sized partitions. In another, the plurality of partitioned test pattern subsets are divided in unequal sized partitions. In another embodiment, unequal sized partitions are ordered in a sequence of patterns based on a determination of effectiveness of the tests. In yet another embodiment, the unequal sized partitions can be reordered with shorter test patterns ordered first in a sequence of patterns.
In one embodi
Huott William V.
Kusko Mary P.
O'Malley Gregory
Robbins Bryan J.
De'cady Albert
International Business Machines - Corporation
Lynn Augspurger Cantor Colburn LLP
Torres Joseph
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