Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-29
2002-12-24
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S714000, C324S073100
Reexamination Certificate
active
06499126
ABSTRACT:
This patent application claims priority based on a Japanese patent application, H11-184470 filed on Jun. 29, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern generator and an electric part testing apparatus which generates a test pattern used for testing an electric part.
2. Description of the Related Art
Conventionally, an electric part testing apparatus used for testing an electric part such as semiconductor memory comprises a pattern generator, which generates a test pattern used for testing an electric part.
FIG. 1
shows a configuration of a conventional pattern generator. A pattern generator
100
generates a test pattern for a dynamic random access memory (DRAM), which is an example of an electric part.
A pattern generator
100
has a vector memory
102
, a read out controller
103
, a vector cache memory
104
, an address expansion unit
106
, an address designating unit (AP)
108
, a timer
110
, an interruption controller
112
, a refresh address-designating unit (SPI)
114
, a multiplexer (MUX)
116
, and a pattern-generating unit
118
. A timer
110
generates an interruption request for every predetermined time interval. The interruption controller
112
sets a refresh cycle signal (REF CYCLE) to “1” and outputs to an address expansion unit
106
and a multiplexer
116
on receipt of the interruption request from the timer
110
.
The vector memory
102
is constituted by a mass storage static random access memory, SRAM, and stores a vector instruction (sequence instruction) that defines an order for reading out a control instruction, which defines a test pattern to be generated.
The read out controller
103
inputs a part of the vector instruction from the vector memory
102
and outputs the input vector instruction to the vector cache memory
104
. The vector cache memory
104
is constituted by a small storage high speed SRAM, and stores a vector instruction input from the read out controller
103
. Furthermore, the vector cache memory
104
outputs the vector instruction to the address expansion unit
106
based on the address, which is input from the address-designating unit
108
.
The address expansion unit
106
generates an address by interpreting the vector instruction input from the vector cache memory
104
and outputs the generated address to the address-designating unit
108
. Moreover, the address expansion unit
106
interrupts the generation of the address when the refresh cycle signal, which is set to “1”, is input from the interruption controller
112
. The address expansion unit
106
restarts the generation of the address when the refresh cycle signal, which is set to “0”, is input from the interruption controller
112
. The address-designating unit
108
stores and outputs the address input from the address expansion unit
106
.
The refresh address-designating unit
114
stores and outputs an address, which corresponds to the control instruction for refreshing an electric part. The multiplexer
116
selects either the address input from the interruption controller
112
or the address input from the refresh address-designating unit
114
, based on the refresh cycle signal input from the interruption controller
112
. The address input from the refresh address-designating unit
114
is selected when the refresh cycle is “1”, and the address input from the address-designating unit
108
is selected when the refresh cycle signal is “0”.
The pattern-generating unit
118
has a control instruction memory
120
, pattern operator
122
, a resistor XB, a resistor YB, and a resistor RF. The control instruction memory
120
stores a control instruction, which generates a test pattern, and outputs the control instruction corresponding to the address, which is input from the multiplexer
116
, to pattern operator
122
. The resistor XB stores a value to be provided as a column address of a DRAM, which is an object to be tested. The resistor YB stores a value to be provided as a row address of the DRAM, and the resistor RF stores a row address for refreshing the DRAM. The pattern operator
122
generates a test pattern based on the control instruction output from the control instruction memory
120
. Example of test patterns include, an address signal, a Row Address Strobe (RAS) signal, a Column Address Strobe (CAS) signal, a data signal, and a write enable (/WE: where “/” stands for reverse logic) signal.
FIG. 2
shows various kinds of information stored in the conventional pattern generator. FIG.
2
(A) shows an address stored in the refresh address-designating unit
114
. The refresh address-designating unit
114
stores “1#300” as an address corresponding to the refresh controlling instruction. FIG.
2
(B) shows a sequence instruction stored in the vector memory
102
. In FIG.
2
(B), “NOP” is an instruction that outputs the present address value and advances the address value to the next value, that is, adds “1” to the present address value. “JNI STO” is an instruction that outputs the present address value and executes the instruction of the address, which is allotted a label STO.
FIG.
2
(C) shows a part of a control instruction stored in the control-instruction memory
118
. In FIG.
2
(C), “XB<0” is an instruction that clears the value of the resistor XB to “0” in the next cycle. “XB<XB+1” is an instruction that adds “1” to the value of the resistor XB in the next cycle. “YB<0” is an instruction that clears the value of the resistor YB to “0” in the next cycle. “YB<YB+1” is an instruction that adds “1” to the value of the resistor YB in the next cycle. “RF<RF+1” is an instruction that adds “1” to the value of the resistor RF in the next cycle.
“PAGE-IN” is an instruction that outputs a signal to the DRAM for inputting a row address and a column address, which executes the data writing process or data reading process. For example, “PAGE-IN” is an instruction that outputs the value of the resistor YB as an address signal and outputs a RAS signal, which is set to LOW, and also outputs the value of the resistor XB as an address signal and outputs the CAS signal, which is set to a negative pulse. “PAGE” is an instruction that outputs the signal to the DRAM for changing a column address, which executes the data writing process or data reading process. For example, “PAGE” is an instruction that outputs the value of the resistor as an address signal and outputs the CAS signal, which is set to a negative pulse.
“PAGE-OUT” is an instruction that outputs a signal to the DRAM for terminating the data reading process or data writing process. For example, “PAGE-OUT” is an instruction that outputs the value of the resistor XB as an address signal, and a CAS signal which is set to a negative pulse, and also outputs the RAS signal, which is set to HIGH. By setting the RAS signal to HIGH, the DRAM is pre-charged. That is, the wiring capacity of the DRAM is charged. “REFRESH” is an instruction that outputs a signal for executing the refreshing operation on the DRAM. For example, “REFRESH” is an instruction that outputs the value of the resistor RF as an address signal and outputs a RAS signal, which is set to LOW.
FIG. 3
shows an operation of the conventional pattern generator.
FIG. 3
shows an operation of the pattern generator
100
when the several kinds of information shown in
FIG. 2
are stored in the pattern generator. FIG.
3
(A) shows a value of an address output from the address-designating unit
108
, a value of the address PC output from the multiplexer
116
, the value of the resistor XB, the value of the resistor YB, the value of the resistor RF, the value of the refresh cycle (REFCYCLE), the operation of the resistor, which is a provider of the address output to the DRAM, and the operation of the DRAM for each cycle during the operation of the pattern generator. FIG.
3
(B) shows a signal, which is output to the DRAM from the pattern generator, from the cycle
6
to cycle
11
.
In the cycle
1
, the add
Advantest Corporation
Moise Emmanuel L.
Rosenthal & Osha L.L.P.
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