PCI express physical layer built-in self test architecture

Details PCI express physical layer built-in self test architecture PCI express physical layer built-in self test architecture

2005-08-30

2009-02-10

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S704000, C714S712000

Reexamination Certificate

active

07490278

ABSTRACT:
A built-in self test circuit includes a first pattern generator, an elastic buffer receiver, a command symbol detector, a second pattern generator, and a logic unit. The architecture is capable of compensating loopback latency automatically without having to utilize a device that stores test patterns generated by the first pattern generator, and error warning can be greatly reduced. Also, the architecture can reduce the effect of phase jitter and error rate count is provided. Hence, accuracy of test can be increased.

REFERENCES:
patent: 6574758 (2003-06-01), Eccles
patent: 7062688 (2006-06-01), Gauthier et al.
patent: 2004/0044938 (2004-03-01), Heo

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