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Built-in-self-repair arrangement for a single...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Built-in-self-test circuit for RAMBUS direct RDRAM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Built-in-self-test using embedded memory and processor in an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Built-in-test diagnostic and maintenance support system and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Burn in technique for chips containing different types of IC cir

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Burn-in test circuit, burn-in test method, burn-in test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Bus mastering debugging system for integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Bypassing a device in a scan chain

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Calibration method and apparatus for correcting pulse width...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Calibration system that can be utilized with a plurality of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Capturing and evaluating high speed data streams

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Centralized BIST engine for testing on-chip memory structures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Centralized BIST engine for testing on-chip memory structures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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CGROM testing device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Changing scan paths shifting by changing mode select input...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Characterizing jitter sensitivity of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Chip performance optimization with self programmed built in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Chip testing apparatus and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Chip testing system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit and method for adding parametric test capability to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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