Changing scan paths shifting by changing mode select input...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S727000, C714S729000

Reexamination Certificate

active

08001436

ABSTRACT:
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

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patent: 6158032 (2000-12-01), Currier et al.
patent: 6594802 (2003-07-01), Ricchetti et al.
patent: 6694467 (2004-02-01), Whetsel
Chakravarty, S.; Dabholkar, V.P.; , “Two techniques for minimizing power dissipation in scan circuits during test application,” Test Symposium, 1994., Proceedings of the Third Asian , vol., No., pp. 324-329, Nov. 15-17, 1994 doi: 10.1109/ATS.1994.367211 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=367211&isnumber=8409.

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