Chip testing system

Details Chip testing system Chip testing system

1999-03-26

2002-01-01

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S811000

Reexamination Certificate

active

06336198

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a chip testing system for testing the quality of chips, and more particularly to such a chip testing system which avoids reading in the conflict in the turn-around cycle between input mode and output mode by masking the conflict with a blanking signal obtained from an internal signal from the chip under test.
When a chip is fabricated, it must be tested before dispatching from the factory. The procedure of testing the quality of a chip through a regular tester is achieved by: using the channel of the tester to apply a test pattern to the chip through its I/O pin, then reading in output data from the I/O pin of the chip for comparison with expected value, and then making a quality judgment subject to the comparison result.
FIG. 1
is a waveform chart obtained from the test of a chip through a conventional tester. During test, the tester uses a cycle signal with a test cycle of constant frequency to make test. As illustrated, a conflict occurs in the turn-around cycle between input mode and output mode. This happening may causes a damage to the chip and/or the tester. If state machine (SM) control signal comes from the pad of the chip, SM control signal is unstable in this turn-around cycle, thereby causing the state machine unable to work normally.
SUMMARY OF THE INVENTION
The present invention has been accomplished to provide a chip testing system which eliminates the aforesaid problems by avoiding to read in the conflict in the turn-around cycle between input mode and output mode during test. It is one object of the present invention to provide a chip test method which eliminates the occurrence of a conflict in the turn-around cycle between input mode and output mode when testing a chip. It is another object of the present invention to provide a chip testing circuit which avoid the occurrence of a conflict in the turn-around cycle between input mode and output mode when testing a chip. It is still another object of the present invention to provide a conflict eliminating chip testing circuit which can be built in the chip. The present invention uses the preceding signal, posterior signal and reverse phase signal of the output enable signal of the chip under test to match with a testing circuit for producing a blanking signal, which is driven only when the output enable signal is at a high potential, enabling the state machine in the chip to control data reading time, so as to avoid a conflict in the turn-around cycle between input mode and output mode.


REFERENCES:
patent: 3924144 (1975-12-01), Hadamard
patent: 4730317 (1988-03-01), Desyllas et al.
patent: 5610926 (1997-03-01), Marris

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