Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-15
2002-12-17
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
06496953
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to automated test equipment for testing integrated electronic circuits, and more particularly to correcting for pulse width timing errors in such equipment.
BACKGROUND
Automated test equipment (ATE) is used for testing (e.g., in a semiconductor chip fabrication facility) to simulate the operating conditions that an integrated circuit (chip) will experience when used in the field. An integrated circuit undergoing testing is also known as a device under test (DUT).
The ATE is controlled by an associated computer or processor which executes a set of instructions (the test program). The ATE must supply signals having the correct voltages, currents, timings and functional states to the DUT and monitor the responses from the DUT. The ATE then compares the responses from each test to pre-defined limits and a pass/fail decision is made.
A test “event” is a pair expressed as the notation (S, T) where “S” is a functional state and “T” is the time associated with the transition to S. An “event sequence” is a time-ordered list of such pairs. For example, in the signal waveform shown in
FIG. 1
, the event sequence has four events expressed as (D
1
,
3
), (D
0
,
7
), (D
1
,
10
), and (D
0
,
14
). The first event drives the signal to a high state (
1
) at time=3 nanoseconds (ns). The second event drives the signal to a low state (
0
) at time=7 ns. The third event drives to a high at time=10 ns and the fourth event drives to a low at time=14 ns. (“Amplitude” in
FIG. 1
is a signal voltage which is set by the test program.)
The first two events can be said to describe a pulse
101
—a transient signal that is of short duration, and one polarity. The pulse has a leading edge
103
and a trailing edge
105
. The pulse width, or pulse duration, is the time interval between points on the leading and trailing edges at a specific voltage value, usually the time interval between the half amplitude points of the pulse. Thus, the pulse width of pulse
101
is about 4 nanoseconds (ns). Similarly, the pulse width of pulse
107
is about 4 ns.
ATE signals are affected by many error sources, but among the most significant in high performance testers is an error related to pulse width, as shown in FIG.
2
. As the intended (nominal) pulse width becomes smaller, it becomes less likely that the pulse will reach full amplitude before it is instructed by the tester to reverse itself. Therefore, the trailing edge of the pulse occurs earlier than desired. The actual pulse width is less than the nominal pulse width, and a timing error results. Line
205
depicts the error curve, which indicates that the timing error increases as nominal pulse width decreases. The error curve could be more erratic, as shown in line
207
. As long as the error curve is predictable, however, pulse width timing error could be accounted for. A pulse width timing error has been found to occur on a particular tester when the pulse width is decreased to 1.25 ns or less. Thus, the second of two timing edges that are intended to be 1 ns apart will have a timing error if and only if the following 3 conditions are satisfied: 1) 1 ns is sufficiently small to cause the small pulse error for the circuit; 2) the first edge actually caused a transition in the state of functional data; and 3) the second edge is of opposite polarity from the first.
Conditions 2) and 3) above imply that there can be no pulse width (and hence no small pulse width timing error) unless there is a transition in functional states being sent from the driver circuit of the tester to a terminal of the DUT. Accordingly, pulse width error is a function of the functional data stream arriving at the terminal of the DUT. Consider, for example, a sequence of functional data (F
1
-F
8
) “01111010”, each datum being instructed by the tester to occur in this order at 1 ns intervals on a terminal of the DUT. The waveform corresponding to this sequence of functional data is shown in FIG.
3
. In this case, datum F
5
does not cause a transition, so has no pulse width. F
6
causes a transition from 1 to 0 and has a pulse width of 4 ns. F
7
causes a transition from 0 to 1 and has a pulse width of 1 ns. F
8
causes a transition from 1 to 0 and has a pulse width of 1 ns. There is no pulse width timing error associated with F
5
, because there is no transition in functional state. There is no significant pulse width timing error associated with F
6
, because, though there is a transition in functional state, the pulse width here is 4 ns, which is greater than the critical value of 1.25 ns. F
6
is said to be ending a pulse, but not a “short” pulse (a pulse is herein termed a “short” pulse if it is 1.25 ns or less in duration). There is a pulse width timing error associated with F
7
, because it causes a transition in functional state, and has a pulse width of 1 ns. F
7
is said to be ending a short pulse. Similarly, there is a pulse width timing error associated with F
8
, because (like F
7
) it causes a transition in functional state and has a pulse width of 1 ns. Thus, F
8
is also said to be ending a short pulse. This pulse width timing error has been found to be on the order of 30 picoseconds (ps), when the functional data occurs at 1 ns intervals. Pulse width error increases with the frequency of functional data output. For example, when the functional data occurs at 800 ps intervals, the pulse width error grows to 50 ps. As mentioned above, a pulse width timing error has been found to occur on a particular tester when the pulse width is decreased to 1.25 ns or less. Thus, to determine whether the second of two timing edges (represented by a bit of functional data) that are programmed to be 1 ns apart has a pulse width timing error, the bit of functional data must be analyzed in view of the two bits that precede it. For example, F
2
, F
3
, and F
4
are required to determine the pulse width prior to F
4
.
There is a need to be able to correct for this pulse width timing error, especially during testing of high performance integrated circuits. For example, the very high frequency of RAMBUS 64/72 Mbit DRAM (dynamic random access memory conforming to the RAMBUS standard) demands extremely accurate testers to successfully test the devices; a timing edge placement accuracy (EPA) of +/−50 picoseconds (ps) is required. Presently, no solution has been put forward to solve this problem.
SUMMARY
The present invention is directed to methods of and apparatus for correcting for pulse width timing errors as described above. According to the current art, a test program first loads scrambler and sequencer memories (each terminal of a DUT having associated with it one of each of these memories) with information representing event timing values and event type data for the events that are to occur during a test vector, (as in the well known Schlumberger Sequencer Per Pin® architecture).
A method for correcting for pulse width timing error during testing of an integrated circuit is described. The method includes storing in a memory, associated with a selected terminal of an integrated circuit, event timing data pertaining to testing of the integrated circuit. Functional data is provided, pertaining to the testing, and it is determined if the functional data causes a state transition in the integrated circuit, the state transition causing a pulse. If a pulse is created, then the event timing data is adjusted, thereby to produce pulse width adjusted event timing. A test signal is then applied to the selected terminal of the integrated circuit, the test signal including pulse width adjusted event timing.
Two apparata for implementing the method of the present invention are herein described. One apparatus implements single value pulse width calibration. In one embodiment of this apparatus, the elements include a decoder, a source of functional data having an output terminal coupled to the decoder, and also having a second output terminal. Also included is an event sequencer, having a first set of storage locations asso
Chung Phung M.
Klivans Norman R.
Schlumberger Technologies Inc.
Skjerven Morrill LLP
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