Circuit and method for adding parametric test capability to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S734000

Reexamination Certificate

active

10414309

ABSTRACT:
A boundary scan cell for use in a circuit having a boundary scan shift register (BSSR) having boundary scan cells associated with pins of the circuit, the cell having a single-bit shift register element and an associated update latch, comprises a logic circuit for controlling the logic state of an associated pin, analog switches connecting the associated pin to analog test buses, and logic circuitry for selectively configuring the cell in a parametric test mode in which the cell shift register element controls the analog switches, and in a digital test mode in which the cell shift register element controls the logic state of the associated pin.

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Lofstrom, Keith, “A Demonstration IC for the P1149.4 Mixed Signal Test Standard”, 1996 ITC Proceedings.
Parker et. al., “Design, Fabrications and Use of Mixed-Signal IC Testability Structures”, 1997 ITC Proceedings.

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