Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-12-01
2009-06-02
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S700000, C714S744000
Reexamination Certificate
active
07543209
ABSTRACT:
Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.
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Office Action (Mail Date Jan. 23, 2008) for U.S. Appl. No. 11/583,048, filed Oct. 6, 2006; Confirmation No. 7134.
Office Action (Mail Date Jul. 14, 2008) for U.S. Appl. No. 11/583,048, filed Oct. 6, 2006; Confirmation No. 7134.
Bonneau Dominique P
Hauviller Philippe
Vallet Vincent
Abraham Esaw T
Canale Anthony J.
International Business Machines - Corporation
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